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? 2016 microchip technology inc. ds00002275a-page 1 features ? single-chip 10base-t/1 00base-tx ieee 802.3 compliant ethernet transceiver ? mii interface support (ksz8091mnx) ? rmii v1.2 interface support with a 50 mhz refer- ence clock output to mac, and an option to input a 50 mhz reference clock (ksz8091rnb) ? back-to-back mode support for a 100 mbps cop- per repeater ? mdc/mdio management interface for phy reg- ister configuration ? programmable interrupt output ? led outputs for link and activity status indica- tion, plus speed indication for ksz8091rnb ? on-chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi-x to reliably detect and cor- rect straight-through and crossover cable con- nections with disable and enable option ? auto-negotiation to automatically select the highest link-up speed (10/100 mbps) and duplex (half/full) ? energy efficient ethernet (eee) support with low-power idle (lpi) mode and clock stoppage (mii version only) for 10 0base-tx and transmit amplitude reduction with 10base-te option ? wake-on-lan (wol) support with either magic packet, link status change, or robust custom- packet detection ? hbm esd rating (6 kv) ? power-down and power-saving modes ? linkmd ? tdr-based cable diagnostics to iden- tify faulty copper cabling ? parametric nand tree support for fault detec- tion between chip i/os and the board ? loopback modes for diagnostics ? single 3.3v power supply with v dd i/o options for 1.8v, 2.5v, or 3.3v ? built-in 1.2v regulator for core ? available in 32-pin 5 mm x 5 mm qfn package target applications ? game consoles ? ip phones ? ip set-top boxes ?ip tvs ?lom ? printers ksz8091mnx/rnb 10base-t/100base-tx physical layer transceiver
ksz8091mnx/rnb ds00002275a-page 2 ? 2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2016 microchip technology inc. ds00002275a-page 3 ksz8091mnx/rnb table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 pin description and configuration ......................................................................................... ......................................................... 5 3.0 functional description .................................................................................................... .............................................................. 15 4.0 register descriptions ..................................................................................................... ............................................................... 40 5.0 operational charac teristics ............................................................................................... ............................................................ 57 6.0 electrical characteristics ................................................................................................ ............................................................... 58 7.0 timing diagrams ........................................................................................................... ................................................................ 60 8.0 reset circuit ............................................................................................................. .................................................................... 69 9.0 reference circuits ? le d strap-in pins .................................................................................... .................................................. 70 10.0 reference clock - connection and selection ............................................................................... .............................................. 71 11.0 magnetic - connection and selection ...................................................................................... ................................................... 72 12.0 package outline .......................................................................................................... ................................................................ 74 appendix a: data sheet revision history ....................................................................................... .................................................... 75 the microchip web site ........................................................................................................ .............................................................. 76 customer change notification service .......................................................................................... ..................................................... 76 customer support .............................................................................................................. ................................................................. 76 product identification system ................................................................................................. ............................................................ 77
ksz8091mnx/rnb ds00002275a-page 4 ? 2016 microchip technology inc. 1.0 introduction 1.1 general description the ksz8091 is a single-supply 10base- t/100base-tx ethernet physical-laye r transceiver for transmission and reception of data over standard cat-5 unshielded twisted pair (utp) cable. the ksz8091 is a highly integrated phy solution. it reduce s board cost and simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low- noise regulator to supply the 1.2v core, and by offering a flexible 1.8/2.5/3.3v digital i/o interface. the ksz8091mnx offers the media independent interface (mii) and the ksz8091rnb offers the reduced media inde- pendent interface (rmii) for direct connection with mii/ rmii-compliant ethernet ma c processors and switches. energy efficient ether net (eee) provides further power saving during idle traffic peri ods and wake-on-lan (wol) pro- vides a mechanism for the ksz8091 to wake up a system that is in standby power mode. the ksz8091 provides diagnostic features to facilitate system bring-up and debugging in production testing and in prod- uct deployment. parametric nand tree support enables fault detection between ksz8091 i/os and the board. linkmd ? tdr-based cable diagnostics identify faulty copper cabling. the ksz8091mnx and ksz8091rnb are available in 32-pin, lead-free qfn packages. figure 1-1: system block diagram ksz8091mnx/ ksz8091rnb magnetics rj-45 connector media types: 10base-t 100base-tx on-chip termination resistors mii/rmii mdc/ mdio management xo xi 25mhz xtal 22pf 22pf 10/100mbps mii/rmii mac 50mhz (ksz8091rnb) ref_clk pme_n (system power circuit)
? 2016 microchip technology inc. ds00002275a-page 5 ksz8091mnx/rnb 2.0 pin description and configuration figure 2-1: 32-pin 5 mm x 5 mm qfn assignment, ksz8091mnx (top view) table 2-1: signals - ksz8091mnx pin number pin name type note 2-1 description 1 gnd gnd ground. 2 vdd_1.2 p 1.2v core v dd (power supplied by ksz8091mnx) decouple with 2.2 f and 0.1 f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4rxmi/o physical receive or transmit signal (? differential) 5rxpi/o physical receive or transmit signal (+ differential) gnd vdd_1.2 vdda_3.3 rxm rxp txm txp xo rxd3/phyad0 mdc mdio rext xi rxd2/phyad1 rxd1/phyad2 rxd0/duplex 1 2 3 4 5 6 7 8 91011121314 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 txd0 txen txc/pme_en intrp/pme_n2/nand_tree# rxer/iso rxc/b-cast_off rxdv/config2 vddio col/config0 crs/config1 led0/pme_n1/nwayen txer rst# txd3 txd2 txd1 paddle ground (on bottom of chip)
ksz8091mnx/rnb ds00002275a-page 6 ? 2016 microchip technology inc. 6txmi/o physical transmit or receive signal (? differential) 7txpi/o physical transmit or receive signal (+ differential) 8xoo crystal feedback for 25 mhz crystal this pin is a no connect if an oscilla tor or external clock source is used. 9xii crystal/oscillator/external clock input 25 mhz 50 ppm 10 rext i set phy transmit output current connect a 6.49 k ? resistor to ground on this pin. 11 mdio ipu/ opu management interface (mii) data i/o this pin has a weak pull-up, is open-drain, and requires an external 1.0 k ? pull-up resistor. 12 mdc ipu management interface (mii) clock input this clock pin is synchronous to the mdio data pin. 13 rxd3/ phyad0 ipu/o mii mode: mii receive data output[3] ( note 2-2 ) config mode: the pull-up/pull-down val ue is latched as phyaddr[0] at the de assertion of reset. see the strap-in options - ksz8091mnx section for details. 14 rxd2/ phyad1 ipd/o mii mode: mii receive data output[2] ( note 2-2 ) config mode: the pull-up/pull-down val ue is latched as phyaddr[1] at the deassertion of reset. see the strap-in options - ksz8091mnx section for details. 15 rxd1/ phyad2 ipd/o mii mode: mii receive data output[1] ( note 2-2 ) config mode: the pull-up/pull-down val ue is latched as phyaddr[2] at the de assertion of reset. see the strap-in options - ksz8091mnx section for details. 16 rxd0/ duplex ipu/o mii mode: mii receive data output[0] ( note 2-2 ) config mode: the pull-up/pull-down val ue is latched as duplex at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. 17 vddio p 3.3v, 2.5v, or 1.8v digital v dd 18 rxdv/ config2 ipd/o mii mode: mii receive data valid output config mode: the pull-up/pull-down value is latched as config2 at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. 19 rxc/ b-cast_off ipd/o mii mode: mii receive clock output config mode: the pull-up/pull-down val ue is latched as b-cast_off at the de assertion of reset. see the strap-in options - ksz8091mnx section for details. 20 rxer/iso ipd/o mii mode: mii receive error output config mode: the pull-up/pull-down value is latched as isolate at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. table 2-1: signals - ksz8091mnx (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002275a-page 7 ksz8091mnx/rnb 21 intrp/ pme_n2/ nand_tree# ipu/ opu interrupt output: programmable interrupt output, with register 1bh as the interrupt control/status register, for programming the interrupt conditions and reading the interrupt status. register 1fh, bit [9] sets the interrupt output to active low (default) or active high. pme_n output: programmable pme_n ou tput (pin option 2). when asserted low, this pin signals that a wol event has occurred. config mode: the pull-up/pull-down value is latched as nand tree# at the deassertion of reset. see the strap-in options - ksz8091mnx section for details. this pin has a weak pull-up and is an open-drain. for interrupt (when active low) and pme functions, this pin requires an exter- nal 1.0 k ? pull-up resistor to v ddio (digital v dd ). 22 txc/ pme_en ipd/o mii mode: mii transmit clock output mii back-to-back mode: no connection config mode: the pull-up/pull-down value is latched as pme_en at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. 23 txen i mii mode: mii transmit enable input 24 txd0 i mii mode: mii transmit data input[0] ( note 2-3 ) 25 txd1 i mii mode: mii transmit data input[1] ( note 2-3 ) 26 txd2 i mii mode: mii transmit data input[2] ( note 2-3 ) 27 txd3 i mii mode: mii transmit data input[3] ( note 2-3 ) 28 col/ config0 ipd/o mii mode: mii collision detect output config mode: the pull-up/pull-down value is latched as config0 at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. 29 crs/ config1 ipd/o mii mode: mii carrier sense output config mode: the pull-up/pull-down value is latched as config1 at the de- assertion of reset. see the strap-in options - ksz8091mnx section for details. table 2-1: signals - ksz8091mnx (continued) pin number pin name type note 2-1 description
ksz8091mnx/rnb ds00002275a-page 8 ? 2016 microchip technology inc. note 2-1 p = power supply gnd = ground i = input o = output i/o = bi-directional ipu = input with internal pull-up (see electrical characteristics for value). ipd = input with internal pull-down (see electrical characteristics for value). ipu/o = input with in ternal pull-up (see electrical characteristics for value) duri ng power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (see electrical characteristics for value) and output with internal pull-up (see electrical characteristics for value). note 2-2 mii rx mode: the rxd[3: 0] bits are synchronous with rxc. when rxdv is asserted, rxd[3:0] presents valid data to the mac. 30 led0/ pme_n1/ nwayen ipu/o led output: programmable led0 output pme_n output: programmable pme_n output (pin option 1) in this mode, this pin has a weak pu ll-up, is an open-drain, and requires an external 1.0 k ? pull-up resistor to v ddio (digital v dd ). config mode: latched as aut o-negotiation enable (regist er 0h, bit [12]) at the de-assertion of reset. see the strap-in options - ksz8091mnx section for details. the led0 pin is programmable using register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11]: reserved 31 txer ipd mii mode: mii transmit error input for eee mode, this pin is driven by the eeemac to pull up this pin for ksz8091mnx transmit into the lpi state. for non-eee mode, this pin is not defined for error transmission from mac to ksz8091mnx and can be left as a no connect. for nand tree testing, this pin should be pulled high by a pull-up resistor. 32 rst# ipu chip reset (active low) paddle gnd gnd ground table 2-1: signals - ksz8091mnx (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002275a-page 9 ksz8091mnx/rnb note 2-3 mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3:0] presents valid data from the mac. the strap-in pins are latched at the de-assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power-up or reset, and consequently caus e the phy strap-in pins on t he mii signals to be latched to unintended high/low states. in this case, external pull-ups (4.7 k ? ) or pull-downs (1.0 k ? ) should be added on these phy strap-in pins to ensure that the intended values are strapped-in correctly. note 2-4 ipu/o = input with internal pull-up duri ng power-up/reset; output pin otherwise. ipd/o = input with internal pull-down du ring power-up/reset; output pin otherwise. ipu/opu = input with internal pull- up and output with internal pull-up. table 2-2: strap-in options - ksz8091mnx pin number pin name type note 2-4 description 15 phyad2 ipd/o phyad[2:0] is latched at de-a ssertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy address, but it can be assigned as a unique phy address after pull- ing the b-cast_off strapping pin high or writing a ?1? to register 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 14 phyad1 ipd/o 13 phyad0 ipu/o 18 config2 ipd/o the config[2:0] strap-in pins are latched at the de-assertion of reset. 29 config1 config[2:0] mode 000 mii (default) 28 config0 110 mii back-to-back 001 ? 101, 111 reserved, not used 22 pme_en ipd/o pme output for wake-on-lan pull-up = enable pull-down (default) = disable at the de-assertion of re set, this pin value is latched into register 16h, bit [15]. 20 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable at the de-assertion of reset, this pin value is latched into register 0h, bit [10]. 16 duplex ipu/o duplex mode: pull-up (default) = half-duplex pull-down = full-duplex at the de-assertion of reset, this pin value is latched into register 0h, bit [8]. 30 nwayen ipu/o nway auto-negotiation enable: pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation at the de-assertion of reset, this pin value is latched into register 0h, bit [12]. 19 b-cast_off ipd/o broadcast off ? for phy address 0: pull-up = phy address 0 is set as an unique phy address pull-down (default) = phy address 0 is set as a broadcast phy address at the de-assertion of reset, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree mode: pull-up (default) = disable pull-down = enable at the de-assertion of reset, this pin value is latched by the chip.
ksz8091mnx/rnb ds00002275a-page 10 ? 2016 microchip technology inc. figure 2-2: 32-pin 5 mm x 5 mm qfn assignment, ksz8091rnb (top view) table 2-3: signals - ksz8091rnb pin number pin name type note 2-1 description 1 gnd gnd ground. 2 vdd_1.2 p 1.2v core v dd (power supplied by ksz8091rnb) decouple with 2.2 f and 0.1 f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4 rxm i/o physical receive or transmit signal (? differential) 5 rxp i/o physical receive or transmit signal (+ differential) 6 txm i/o physical transmit or receive signal (? differential) 7 txp i/o physical transmit or receive signal (+ differential) 8xoo crystal feedback for 25 mhz crystal this pin is a no connect if an oscillat or or external clock source is used. gnd vdd_1.2 vdda_3.3 rxm rxp txm txp xo phyad0 mdc mdio rext xi phyad1 rxd1/phyad2 rxd0/duplex 1 2 3 4 5 6 7 8 91011121314 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 txd0 txen pme_en intrp/pme_n2/nand_tree# rxer/iso ref_clk/b-cast_off crs_dv/config2 vddio config0 config1 led0/pme_n1/nwayen led1/speed rst# nc nc txd1 paddle ground (on bottom of chip)
? 2016 microchip technology inc. ds00002275a-page 11 ksz8091mnx/rnb 9xii 25 mhz mode:25 mhz 50 ppm crystal /oscillator/external clock input 50 mhz mode: 50 mhz 50 ppm oscillator/external clock input 10 rext i set phy transmit output current connect a 6.49 k ? resistor to ground on this pin. 11 mdio ipu/opu management interface (mii) data i/o this pin has a weak pull-up, is open- drain, and requires an external 1.0 k ? pull-up resistor. 12 mdc ipu management interface (mii) clock input this clock pin is synchronous to the mdio data pin. 13 phyad0 ipu/o the pull-up/pull-down value is latched as phyaddr[0] at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 14 phyad1 ipd/o the pull-up/pull-down value is latched as phyaddr[1] at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 15 rxd1/ phyad2 ipd/o rmii mode: rmii receive data output[1] ( note 2-2 ) config mode: the pull-up/pull-down va lue is latched as phyaddr[2] at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 16 rxd0/ duplex ipu/o rmii mode: rmii receive data output[0] ( note 2-2 ) config mode: the pull-up/pull-down value is latched as duplex at the de- assertion of reset. see the strap-in options - ksz8091rnb section for details. 17 vddio p 3.3v, 2.5v, or 1.8v digital v dd 18 crs_dv/ config2 ipd/o rmii mode: rmii carrier sens e/receive data valid output config mode: the pull-up/pull-down va lue is latched as config2 at the de- assertion of reset. see the strap-in options - ksz8091rnb section for details. 19 ref_clk/ b-cast_off ipd/o rmii mode: 25 mhz mode: th is pin provides the 50 mhz rmii reference clock output to the mac. see also xi (pin 9). 50 mhz mode: this pin is a no connect. see also xi (pin 9). config mode: the pull-up/pull-down valu e is latched as b-cast_off at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 20 rxer/iso ipd/o rmii mode: rmii receive error output config mode: the pull-up/pull-down va lue is latched as isolate at the de- assertion of reset. see the strap-in options - ksz8091rnb section for details. 21 intrp/ pme_n2/ nand_tree# ipu/opu interrupt output: programmable interrupt output, with register 1bh as the interrupt control/status re gister, for programming the interrupt conditions and reading the interrupt status. register 1fh, bit [9] sets the in terrupt output to active low (default) or active high. pme_n output: programmable pme_n output (pin option 2). when asserted low, this pin signals that a wol event has occurred. config mode: the pull-up/pull-down value is latched as nand tree# at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. this pin has a weak pull-up and is an open-drain. for interrupt (when active low) and pme functions, this pin requires an exter- nal 1.0 k ? pull-up resistor to v ddio (digital v dd ). table 2-3: signals - ksz8091rnb (continued) pin number pin name type note 2-1 description
ksz8091mnx/rnb ds00002275a-page 12 ? 2016 microchip technology inc. 22 pme_en ipd/o the pull-up/pull-down value is latched as pme_en at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 23 txen i rmii transmit enable input 24 txd0 i rmii transmit data input[0] ( note 2-3 ) 25 txd1 i rmii transmit data input[1] ( note 2-3 ) 26 nc nc no connect ? this pin is not bonded and can be left floating. 27 nc nc no connect ? this pin is not bonded and can be left floating. 28 config0 ipd/o the pull-up/pull-down value is latched as config0 at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 29 config1 ipd/o the pull-up/pull-down value is latched as config1 at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. 30 led0/ pme_n1/ nwayen ipu/o led output: programmable led0 output pme_n output: programmabl e pme_n output (pin option 1). in this mode, this pin has a weak pull-up, is an o pen-drain, and requires an external 1.0 k ? pull-up resistor to v ddio (digital v dd ). config mode: latched as auto-negotiation enable (register 0h, bit [12]) at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. the led0 pin is programmable using regi ster 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11]: reserved 31 led1/ speed ipu/o led output: programmable led1 output config mode: latched as speed (register 0h, bit [13] ) at the de-assertion of reset. see the strap-in options - ksz8091rnb section for details. the led1 pin is programmable using regi ster 1fh bits [5:4], and is defined as follows. led mode = [00] speed pin state led definition 10base-t high off 100base-tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11]: reserved table 2-3: signals - ksz8091rnb (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002275a-page 13 ksz8091mnx/rnb note 2-1 p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu = input with internal pull-up (see electrical characteristics for value). ipu/o = input with in ternal pull-up (see electrical characteristics for value) duri ng power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (see electrical characteristics for value) and output with internal pull-up (see electrical characteristics for value). nc = pin is not bonded to the die. note 2-2 rmii rx mode: the rxd[1:0] bits are synchronous with the 50 mhz rmii reference clock. for each clock period in which crs_dv is asserted, two bits of recovered data are sent by the phy to the mac. note 2-3 rmii tx mode: the txd[ 1:0] bits are synchronous with the 50 mhz rmii reference clock. for each clock period in which txen is asserted, two bits of data are received by the phy from the mac. the strap-in pins are la tched at the de-assertion of rese t. in some systems, the mac rm ii receive input pins may drive high/low during power-up or reset, and co nsequently cause the phy str ap-in pins on the rmii signals to be latched to unintended high/low states. in this case, external pull-ups (4.7 k ? ) or pull-downs (1.0 k ? ) should be added on these phy strap-in pins to ensure that the intended values are strapped-in correctly. 32 rst# ipu chip reset (active low) paddle gnd gnd ground table 2-4: strap-in options - ksz8091rnb pin number pin name type note 2-4 description 15 phyad2 ipd/o phyad[2:0] is latched at de-a ssertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy address, but it can be assigned as a unique phy address after pull- ing the b-cast_off strapping pin high or writing a ?1? to register 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 14 phyad1 ipd/o 13 phyad0 ipu/o 18 config2 ipd/o the config[2:0] strap-in pins are latched at the de-assertion of reset. 29 config1 config[2:0] mode 000 rmii (default) 28 config0 110 rmii back-to-back 001 ? 101, 111 reserved, not used 22 pme_en ipd/o pme output for wake-on-lan pull-up = enable pull-down (default) = disable at the de-assertion of re set, this pin value is latched into register 16h, bit [15]. table 2-3: signals - ksz8091rnb (continued) pin number pin name type note 2-1 description
ksz8091mnx/rnb ds00002275a-page 14 ? 2016 microchip technology inc. note 2-4 ipu/o = input with internal pull-up duri ng power-up/reset; output pin otherwise. ipd/o = input with internal pull-down du ring power-up/reset; output pin otherwise. ipu/opu = input with internal pull- up and output with internal pull-up. 20 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable at the de-assertion of reset, this pin value is latched into register 0h, bit [10]. 31 speed ipu/o speed mode pull-up (default) = 100 mbps pull-down = 10 mbps at the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. 16 duplex ipu/o duplex mode: pull-up (default) = half-duplex pull-down = full-duplex at the de-assertion of reset, this pin value is latched into register 0h, bit [8]. 30 nwayen ipu/o nway auto-negotiation enable: pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation at the de-assertion of reset, this pin value is latched into register 0h, bit [12]. 19 b-cast_off ipd/o broadcast off ? for phy address 0: pull-up = phy address 0 is set as an unique phy address pull-down (default) = phy address 0 is set as a broadcast phy address at the de-assertion of reset, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree mode: pull-up (default) = disable pull-down = enable at the de-assertion of reset, this pin value is latched by the chip. table 2-4: strap-in options - ksz8091rnb (continued) pin number pin name type note 2-4 description
? 2016 microchip technology inc. ds00002275a-page 15 ksz8091mnx/rnb 3.0 functional description the ksz8091 is an in tegrated single 3.3v supply fast ethernet transceiver. it is fully compliant with the ieee 802.3 specification, and reduces board cost and simplifies board layout by usin g on-chip termination resistors for the two dif- ferential pairs and by integrating the regulator to supply the 1.2v core. on the copper media side, the ksz8091 supports 10base-t and 100base-tx for transmission and reception of data over a standard cat-5 unshielded twisted pair (utp) cable, and hp auto mdi/mdi-x for reliable detection of and cor- rection for straight-through and crossover cables. on the mac processor side, the ksz8091mnx offers t he media independent interfac e (mii) and the ksz8091rnb offers the reduced media independent inte rface (rmii) for direct connection wit h mii and rmii compliant ethernet mac processors and switches, respectively. the mii management bus option gives the mac processor comp lete access to the ksz8091 control and status regis- ters. additionally, an interrupt pin eliminates the n eed for the processor to poll for phy status change. the ksz8091mnx/rnb is used to refer to both ks z8091mnx and ksz8091rnb versions in this data sheet. 3.1 10base-t/100base-tx transceiver 3.1.1 100base-tx transmit the 100base-tx transmit function performs parallel-to-s erial conversion, 4b/5b encoding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, wh ich converts the mii/rmii data from the mac into a 125 mhz serial bit stream. the data and control stream is then conv erted into 4b/5b coding and followed by a scrambler. the serialized data is further converted fr om nrz-to-nrzi format, and then transmitte d in mlt3 current output. the output current is set by an external 6.49 k ? 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and co mplies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timi ng jitter. the wave-shaped 10ba se-t output is also incorp orated into the 100base-tx transmitter. 3.1.2 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrz i conversion, data and clock recovery, nrzi-to-nrz conversi on, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to com pensate for inter-symbol interfer ence (isi) over the twisted pair cable. because the amplitude loss a nd phase distortion is a function of the cable length, the equ alizer must adjust its characteristics to optimize performanc e. in this design, the variable equaliz er makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then t unes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc-restoration and data-conversion block. the dc-restoration circuit com- pensates for the effect of baseline wander and improves the dynamic range. the differential data-conversion circuit con- verts mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock-recovery circuit extracts the 125 mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal to nrz format. this signal is sent through the de-scrambl er, then the 4b/5b decoder. finally, the nrz serial data is converted to mii/rm ii format and provided as the input data to the mac. 3.1.3 scrambler/de-scrambler (100base-tx only) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (emi) and baseline wander. the de-scrambler recovers the scrambled signal. 3.1.4 10base-t transmit the 10base-t drivers are incor porated with the 100base-tx dr ivers to allow for transmi ssion using the same mag- netic. the drivers perform internal wave -shaping and pre-emphasis, and output 10base -t signals with a typical ampli- tude of 2.5v peak for standard 10ba se-t mode and 1.75v peak for energy-e fficient 10base-te mode. the 10base- t/10base-te signals have harmonic conten ts that are at least 27 db below th e fundamental frequency when driven by an all-ones manchester-encoded signal.
ksz8091mnx/rnb ds00002275a-page 16 ? 2016 microchip technology inc. 3.1.5 10base-t receive on the receive side, input buffer and level detecting squelch circuits are used. a differential input receiver circuit and a phase-locked loop (pll) performs the decoding function. t he manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv, or with short pulse widths, to prevent noise at the rxp and rxm inputs from falsely triggering t he decoder. when the input exce eds the squelch limit, the pll locks onto the incoming signal and the ksz8091mnx/rnb decodes a data frame. the receive clock is kept active during idle periods between data receptions. 3.1.6 sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is needed to test the 10base-t transmit/receive path. if transmit e nable (txen) is high for more than 20 ms (jabbering), the 10base-t transmitter is disabled and co l is asserted high. if txen is th en driven low for more than 250 ms, the 10base-t transmitter is re-enabled and col is de-asserted (returns to low). 3.1.7 pll clock synthesizer the ksz8091mnx/rnb ge nerates all internal clocks and all external clocks for system timing from an external 25 mhz crystal, oscillator, or reference clock. for the ksz8091r nb in rmii 50 mhz clock mode, these clocks are generated from an external 50 mhz oscillator or system clock. 3.1.8 auto-negotiation the ksz8091mnx/rnb conforms to the aut o-negotiation protocol, defined in cla use 28 of the ieee 802.3 specifica- tion. auto-negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode of operation. during auto-negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex opera tion mode from highest to lowest priority. ? priority 1: 100base-tx, full-duplex ? priority 2: 100base-tx, half-duplex ? priority 3: 10base-t, full-duplex ? priority 4: 10base-t, half-duplex if auto-negotiation is not s upported or the ksz8091mnx/rnb link partner is forced to bypass auto-negotiation, then the ksz8091mnx/rnb sets its operating mode by observing the si gnal at its receiver. this is known as parallel detection, which allows the ksz8091mnx/rnb to establish a link by listen ing for a fixed signal protocol in the absence of the auto- negotiation advertisement protocol. auto-negotiation is enabled by either hardware pin strapping (nwayen, pin 30) or software (register 0h, bit [12]). by default, auto-negotiation is enabled after power-up or har dware reset. after that, auto-negotiation can be enabled or disabled by register 0h, bit [ 12]. if auto-negotiation is disa bled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. the auto-negotiation link-up process is shown in figure 3-1 .
? 2016 microchip technology inc. ds00002275a-page 17 ksz8091mnx/rnb figure 3-1: auto-ne gotiation flow chart 3.2 mii data interface (ksz8091mnx only) the media independent interface (mii) is compliant with th e ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi- cation). ? 10 mbps and 100 mbps data rates are supported at both half- and full-duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4 bits wide, a nibble. by default, the ksz8091mnx is configured to mii mode afte r it is powered up or hardware reset with the following: ? a 25 mhz crystal connected to xi, xo (pins 9, 8), or an external 25 mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting). start auto-negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto- negotiation link mode set bypass auto- negotiation and set link mode link mode set? parallel operation no yes yes no join flow
ksz8091mnx/rnb ds00002275a-page 18 ? 2016 microchip technology inc. 3.2.1 mii signal definition table 3-1 describes the mii signals. refer to clause 22 of the ieee 802.3 spec ification for detailed information. 3.2.1.1 transmit clock (txc) txc is sourced by the phy. it is a c ontinuous clock that provides the timing reference for txen, txd[3:0], and txer. txc is 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. 3.2.1.2 transmit enable (txen) txen indicates that the mac is presenting nibbles on txd[ 3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii. it is negated before the first txc followin g the final nibble of a frame. txen transitions synchronou sly with respect to txc. 3.2.1.3 transmit data[3:0] (txd[3:0]) when txen is asserted, txd[ 3:0] are the data nibbles pres ented by the mac and accepted by the phy for transmis- sion. when txen is de-asserted, the mac drives txd[3:0] to ei ther 0000 for the idle state (non-eee mode) or 0001 for the lpi state (eee mode). txd[3:0] transitions synchro nously with respect to txc. 3.2.1.4 transmit error (txer) txer is implemented only for the eee function. for eee mode, this pin is driven by the eee-mac to put the ksz8091mnx transmit into the lpi state. for non-eee mode, this pin is not defined for error transm ission from mac to ksz8091mnx and can be left as a no connect. txer transitions synchronou sly with respect to txc. 3.2.1.5 receive clock (rxc) rxc provides the timing referenc e for rxdv, rxd[3:0], and rxer. in 10 mbps mode, rxc is recovered from the line while the carri er is active. when the line is idle or the link is down, rxc is derived from the phy?s reference clock. table 3-1: mii signal definition mii signal name direction with respect to phy, ksz8091mnx signal direction with respect to mac description txc output input transmit clock (2.5 mhz for 10 mbps; 25 mhz for 100 mbps) txen input output transmit enable txd[3:0] input output transmit data[3:0] txer input output or not implemented transmit error (ksz8091mnx implements only the eee function for this pin. see transmit error (txer) for details.) rxc output input receive clock (2.5 mhz for 10 mbps; 25 mhz for 100 mbps) rxdv output input receive data valid rxd[3:0] output input receive data[3:0] rxer output input or not required receive error crs output input carrier sense col output input collision detection
? 2016 microchip technology inc. ds00002275a-page 19 ksz8091mnx/rnb in 100 mbps mode, rxc is continuously recovered from the line. if the link is down, rxc is derived from the phy?s reference clock. rxc is 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. 3.2.1.6 receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. in 10 mbps mode, rxdv is asserted with the first nibble of the start-of-frame delimiter (s fd), 5d, and remains asserted until the end of the frame. in 100 mbps mode, rxdv is asserted from the first ni bble of the preamble to th e last nibble of the frame. rxdv transitions synchronously with respect to rxc. 3.2.1.7 receive data[3:0] (rxd[3:0]) for each clock period in which rxdv is asserted, rxd[ 3:0] transfers a nibble of recovered data from the phy. when rxdv is de-asserted, the phy drives rxd[3:0] to ei ther 0000 for the idle state (non-eee mode) or 0001 for the lpi state (eee mode). rxd[3:0] transitions synchr onously with respect to rxc. 3.2.1.8 receive error (rxer) when rxdv is asserted, rxer is assert ed for one or more rxc periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac sub-la yer) is detected somewhere in the frame that is being transf erred from the phy to the mac. in eee mode only, when rxdv is de-asserted, rxer is driven by the phy to inform the mac that the ksz8091mnx receive is in the lpi state. rxer transitions synchronously with respect to rxc. 3.2.1.9 carrier sense (crs) crs is asserted and de-asserted as follows: ? in 10 mbps mode, crs assertion is based on the receptio n of valid preambles. crs de-assertion is based on the reception of an end-of-frame (eof) marker. ? in 100 mbps mode, crs is asserted when a start-of-stream delimiter or /j/k symbol pair is detected. crs is de- asserted when an end-of-stream delimiter or /t/r symbol pa ir is detected. additional ly, the pma layer de-asserts crs if idle symbols are received without /t/r. 3.2.1.10 collis ion detection (col) col is asserted in half-duplex mode whenever the transmit ter and receiver are simultaneously active on the line. this informs the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc.
ksz8091mnx/rnb ds00002275a-page 20 ? 2016 microchip technology inc. 3.2.2 mii signal diagram the ksz8091mnx mii pin connections to the mac are shown in figure 3-2 . 3.3 rmii data interface (ksz8091rnb only) the reduced media independent interface (rmii) specifies a low pin count me dia independent interface (mii). it pro- vides a common interface between physical layer and mac layer devices, and has the following key characteristics: ? pin count is 8 pins (3 pins for data transmission, 4 pi ns for data reception, and 1 pin for the 50 mhz reference clock). ? 10 mbps and 100 mbps data rates are supported at both half- and full-duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 2 bits wide, a dibit. 3.3.1 rmii - 25 mhz clock mode the ksz8091rnb is configured to rmii - 25 mhz clock mode af ter it is powered up or hardware reset with the following: ? a 25 mhz crystal connected to xi, xo (pins 9, 8), or an external 25 mhz clock source (oscillator) connected to xi. ? the config[2:0] strap-in pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 0 (defau lt value) to select 25 mhz clock mode. 3.3.2 rmii - 50 mhz clock mode the ksz8091rnb is configured to rmii - 50 mhz clock mode af ter it is powered up or hardware reset with the following: ? an external 50 mhz clock source (oscillator) connected to xi (pin 9). ? the config[2:0] strap-in pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 1 to select 50 mhz clock mode. figure 3-2: ksz8091m nx mii interface ' ksz8091mnx txc tx_en txd[3:0] ethernet mac txc txer txer tx_en mii txd[3:0] rxd[3:0] rxd[3:0] rxc rxdv rxc rxdv crs col crs col rxer rxer
? 2016 microchip technology inc. ds00002275a-page 21 ksz8091mnx/rnb 3.3.3 rmii signal definition table 3-2 describes the rmii signals. refer to rmii specification v1.2 for detailed information. 3.3.4 reference clock (ref_clk) ref_clk is a continuous 50 mhz clock t hat provides the timing reference for txen, txd[1:0], crs_dv, rxd[1:0] and rx_er. for 25 mhz clock mode, the ksz8091rnb generates and outputs the 50 mhz rmii ref_clk to the mac at ref_clk (pin 19). for 50 mhz clock mode, the ksz 8091rnb takes in the 50 mhz rmii ref_cl k from the mac or system board at xi (pin 9) and leaves the ref_clk (pin 19) as a no connect. 3.3.5 transmit enable (txen) txen indicates that the mac is presenting dibits on txd[1:0] for transmission. it is asserted synchronou sly with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presen ted on the rmii. it is negated before the first ref_clk followin g the final dibit of a frame. txen transitions synchronousl y with respect to ref_clk. 3.3.6 transmit data[1:0] (txd[1:0]) when txen is asserted, txd[1:0] are the data dibits pres ented by the mac and accepted by the phy for transmission. when txen is de-asserted, the mac drives txd[1:0] to either 00 for the idle state (non-eee mode) or 01 for the lpi state (eee mode). txd[1:0] transitions synchron ously with respect to ref_clk. 3.3.7 carrier sense/receive data valid (crs_dv) the phy asserts crs_dv when the receive medium is non-idle. it is asserted asynchronously when a carrier is detected. this happens when squelch is passed in 10 mbps mode, and w hen two non-contiguous 0s in 10 bits are detected in 100 mbps mode. loss of carrier results in the de-assertion of crs_dv. while carrier detection criteria are met, crs_dv remains asse rted continuously from the first recovered dibit of the frame through the final recovered dibit. it is negated before the first ref_clk th at follows the final dibit. the data on rxd[1:0] is considered valid after crs_dv is asserted. ho wever, because the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is 00 until receive signals are properly decoded. 3.3.8 receive data[1:0] (rxd[1:0]) for each clock period in which crs_dv is asserted, rxd[1: 0] transfers a dibit of recovered data from the phy. when crs_dv is de-asserted, the phy drives rxd[1:0] to either 00 for the idle state (non- eee mode) or 01 for the lpi state (eee mode). rxd[1:0] transitions synchronously with respect to ref_clk. table 3-2: rmii si gnal definition rmii signal name direction with respect to phy ksz8091rnb signal direction with respect to mac description ref_clk output (25 mhz clock mode)/ (50 mhz clock mode) input/input or synchronous 50 mhz reference clock for receive, transmit, and control interface txen input output transmit enable txd[1:0] input output transmit data[1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data[1:0] rxer output input or not required receive error
ksz8091mnx/rnb ds00002275a-page 22 ? 2016 microchip technology inc. 3.3.9 receive error (rxer) when crs_dv is asserted, rxer is asserted for one or mo re ref_clk periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac sub-layer) is detected somewhere in the frame that is being transferred from the phy to the mac. rxer transitions synchronously with respect to ref_clk. 3.3.10 collision detection (col) the mac regenerates the col signal of the mii from txen and crs_dv. 3.3.11 rmii signal diagram the ksz8091rnb rmii pin connections to the mac for 25 mhz clock mode are shown in figure 3-3 . the connections for 50 mhz clock mode are shown in figure 3-4 . figure 3-3: ksz8091rnb rmii in terface (25 mhz clock mode) ksz8091rnb crs_dv rxd[1:0] rxer txd[1:0] rmii mac crs_dv rxd[1:0] txd[1:0] rx_er ref_clk ref_clk txen tx_en xo xi 25mhz xtal 22pf 22pf
? 2016 microchip technology inc. ds00002275a-page 23 ksz8091mnx/rnb 3.4 back-to-back mode ? 100 mbps copper repeater two ksz8091mnx/rnb devices can be connected back- to-back to form a 100base-tx copper repeater. figure 3-4: ksz8091rnb rmii in terface (50 mhz clock mode) figure 3-5: ksz8091mnx/rnb to ks z8091mnx/rnb ba ck-to-back copper repeater ksz8091rnb crs_dv rxd[1:0] rxer txd[1:0] rmii mac crs_dv rxd[1:0] txd[1:0] rx_er ref_clk txen tx_en xi 50mhz osc ksz8091mnx/rnb (copper mode) rxp/rxm txp/txm rxd txd rxd txd osc xi xi 25mhz/ 50mhz txp/txm rxp/rxm (copper mode) ksz8091mnx/rnb
ksz8091mnx/rnb ds00002275a-page 24 ? 2016 microchip technology inc. 3.4.1 mii back-to-back mo de (ksz8091mnx only) in mii back-to-back mode, a ksz8091mnx interfaces with another ksz8091mnx to provide a complete 100 mbps cop- per repeater solution. the ksz8091mnx devices are configured to mii back-to -back mode after power-up or reset with the following: ? strap-in pin config[2:0] (pins 18, 29, 28) set to 110. ? a common 25 mhz reference clock connected to xi (pin 9) of both ksz8091mnx devices. ? mii signals connected as shown in table 3-3 . 3.4.2 rmii back-to-back mo de (ksz8091rnb only) in rmii back-to-back mode, a ksz8091rnb interfaces with another ksz8091rnb to provide a complete 100 mbps copper repeater solution. the ksz8091rnb devices are configured to rmii back-t o-back mode after power-up or reset with the following: ? strap-in pin config[2:0] (pins 18, 29, 28) set to 101. ? a common 50 mhz reference clock connected to xi (pin 9) of both ksz8091rnb devices. ? rmii signals connected as shown in table 3-4 . table 3-3: mii signal connection for mi i back-to-back mode (100base-tx copper repeater) ksz8091mnx (100base-tx copper) [device 1] ksz8091mnx (100base-tx copper) [device 2] pin name pin number pin type pin name pin number pin type rxdv 18 output txen 23 input rxd3 13 output txd3 27 input rxd2 14 output txd2 26 input rxd1 15 output txd1 25 input rxd0 16 output txd0 24 input txen 23 input rxdv 18 output txd3 27 input rxd3 13 output txd2 26 input rxd2 14 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output table 3-4: rmii signal connection fo r rmii back-to-back mode (100base-tx copper repeater) ksz8091rnb (100base-tx copper) [device 1] ksz8091rnb (100base-tx copper) [device 2] pin name pin number pin type pin name pin number pin type crsdv 18 output txen 23 input rxd1 15 output txd1 25 input rxd0 16 output txd0 24 input txen 23 input crsdv 18 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output
? 2016 microchip technology inc. ds00002275a-page 25 ksz8091mnx/rnb 3.5 mii management (miim) interface the ksz8091mnx/rnb supp orts the ieee 802.3 mii management interf ace, also known as the management data input/output (mdio) interface. this interface allows an uppe r-layer device, such as a ma c processor, to monitor and control the state of the ksz8091mnx/rnb. an external devic e with miim capability is used to read the phy status and/ or configure the phy settings. more de tails about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates th e clock line (mdc) and the data line (mdio). ? a specific protocol that o perates across the physical connection mentioned earlier, which allows the external con- troller to communicate with one or more phy devices. ? a 32-register address space for direct access to ieee-de fined registers and vendor-specific registers, and for indi- rect access to mmd addresses and registers. see the register descriptions section. as the default, the ksz8091mn x/rnb supports unique phy addresses 1 to 7, and broadcast phy address 0. the latter is defined in the ieee 802.3 specificat ion, and can be used to read/write to a single ksz8091mnx/rnb device, or write to multiple ksz8091mnx/rnb devices simultaneously. phy address 0 can optionally be disabled as the broadcas t address by either hardware pin strapping (b-cast_off, pin 19) or software (register 16h, bit [9]), and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a unique phy address between 0 and 7 to each ksz8091mnx/rnb device. the miim interface can operates up to a maximum clock speed of 10 mhz mac clock. table 3-5 shows the mii management frame format for the ksz8091mnx/rnb. 3.6 interrupt (intrp) intrp (pin 21) is an optional interrupt signal that is used to inform the external contro ller that there has been a status update to the ksz8091mnx/rnb phy register. bits [15:8] of register 1bh are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. bits [7:0 ] of register 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. bit [9] of register 1fh sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor co mplete access to the ksz8091mnx/rnb control and sta- tus registers. additionally, an interrupt pin eliminates th e need for the processor to poll the phy for status change. 3.7 hp auto mdi/mdi-x hp auto mdi/mdi-x configuration elimi nates the need to decide whether to use a straight cable or a crossover cable between the ksz8091mnx/rnb and its link partner. this fe ature allows the ksz8091mnx/ rnb to use either type of cable to connect with a link partner that is in either mdi or mdi-x mode. the auto-sense function detects transmit and receive pairs from the link partner and assigns transm it and receive pairs to the ksz8091mnx/rnb accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by writing a ?1? to register 1fh, bit [13]. mdi and mdi-x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and rece ive data paths is recommended to support auto mdi/mdi-x. table 3-6 shows how the ieee 802.3 standard defines mdi and mdi-x. table 3-5: mii management frame format for the ksz8091mnx/rnb preamble start of frame read/ write op code phy address bits[4:0] reg address bits[4:0] ta data bits[15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z
ksz8091mnx/rnb ds00002275a-page 26 ? 2016 microchip technology inc. 3.7.1 straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. figure 3-6 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi-x device). 3.7.2 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. figure 3-7 shows a typical crossover cable connection between two switches or hubs (two mdi-x devices). table 3-6: mdi/mdi-x pin description mdi mdi-x rj-45 pin signal rj-45 pin signal 1 tx+ 1 rx+ 2tx?2rx? 3 rx+ 3 tx+ 6 rx? 6 tx? figure 3-6: typical straight cable connection receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch)
? 2016 microchip technology inc. ds00002275a-page 27 ksz8091mnx/rnb 3.8 loopback mode the ksz8091mnx/rnb supports the following loopback opera tions to verify analog and/or digital data paths. ? local (digital) loopback ? remote (analog) loopback 3.8.1 local (dig ital) loopback this loopback mode checks the mii/rmii transmit and receive data paths between the ksz8091mnx/rnb and the external mac, and is supported for bo th speeds (10/100 mbps) at full-duplex. the loopback data path is shown in figure 3-8 . 1. the mii/rmii mac transmits fr ames to the ksz8091mnx/rnb. 2. frames are wrapped around inside the ksz8091mnx/rnb. 3. the ksz8091mnx/rnb transmits fr ames back to the mii/rmii mac. 4. except the frames back to the rmii mac, the tr ansmit frames also go out from the copper port. figure 3-7: typical crossover cable connection receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) crossover cable modular connector (rj-45) hub (repeater or switch)
ksz8091mnx/rnb ds00002275a-page 28 ? 2016 microchip technology inc. the following programming action and register settings are used for local loopback mode: for 10/100 mbps loopback: set register 0h, bit [14] = 1 // enable local loopback mode bit [13] = 0/1 // select 10 mbps/100 mbps speed bit [12] = 0 // disable auto-negotiation bit [8] = 1 // select full-duplex mode 3.8.2 remote (analog) loopback this loopback mode checks the line (differential pairs, tran sformer, rj-45 connector, et hernet cable) transmit and receive data paths between the ksz8091mnx/rnb and its link partner, and is supported for 100base-tx full-duplex mode only. the loopback data path is shown in figure 3-9 . 1. the fast ethernet (1 00base-tx) phy link partner transmit s frames to the ksz8091mnx/rnb. 2. frames are wrapped around inside the ksz8091mnx/rnb. 3. the ksz8091mnx/rnb transmits frames back to the fast ethernet (100base-tx) phy link partner. figure 3-8: local (digital) loopback mii/rmii mac mii/ rmii afe (analog) ksz8091mnx/rnb pcs (digital)
? 2016 microchip technology inc. ds00002275a-page 29 ksz8091mnx/rnb the following programming steps and register settings are used for remote loopback mode: 1. set register 0h, bits [13] = 1 // select 100 mbps speed bit [12] = 0 // disable auto-negotiation bit [8] = 1 // select full-duplex mode or just auto-negotiate and li nk up at 100base-tx full-duplex mode with the link partner. 2. set register 1fh, bit [2] = 1 // enable remote loopback mode 3.9 linkmd ? cable diagnostic the linkmd function uses time-domain reflectometry (tdr) to analyze the cabling plant for common cabling problems. these include open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi-x pair, then analyzing the shape of the reflected signal to determine the type of fault. the time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the linkmd cable diagnostic register, in conjunction with register 1fh, the phy control 2 register. the latter register is used to di sable auto mdi/mdi-x and to select either mdi or mdi-x as the cable differential pair for testing. 3.9.1 usage the following is a sample procedure for using linkmd with registers 1dh and 1fh: 1. disable auto mdi/mdi-x by writing a ?1? to register 1fh, bit [13]. 2. start cable diagnostic test by writing a ?1? to regist er 1dh, bit [15]. this enable bit is self-clearing. 3. wait (poll) for register 1dh, bit [15] to return a ?0?, and indicating cable diagnostic test is completed. 4. read cable diagnostic test results in register 1dh, bits [14:13]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) figure 3-9: remote (analog) loopback rj-45 rj-45 cat-5 (utp) ksz8091mnx/rnb 100base-tx link partner afe (analog) pcs (digital) mii/ rmii
ksz8091mnx/rnb ds00002275a-page 30 ? 2016 microchip technology inc. 11 = cable diagnostic test failed (invalid test) the ?11? case, invalid test, occurs when the device is unable to shut down the link partner. in this instance, the test is not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. get distance to fault by concatenati ng register 1dh, bits [8:0] and multiply ing the result by a constant of 0.38. the distance to the cable fault can be determined by the following formula: equation 3-1: concatenated value of registers 1dh bits [8:0] shoul d be converted to decimal before multiplying by 0.38. the constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. 3.10 nand tree support the ksz8091mnx/rnb provides pa rametric nand tree support for fault de tection between chip i/os and board. the nand tree is a chain of nested nand ga tes in which each ksz8091mnx/rnb digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the crs/config1 pin prov ides the output for the nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially, according to the nand tree pin order ? checking the nand tree output to make sure there is a toggle high-to-low or low-to-high for each nand tree input driven low table 3-7 and ta b l e 3 - 8 list the nand tree pin orders for ksz8091mnx and ksz8091rnb, respectively. table 3-7: nand tree test pin order for ksz8091mnx pin number pin name nand tree description 11 mdio input 12 mdc input 13 rxd3 input 14 rxd2 input 15 rxd1 input 16 rxd0 input 18 rxdv input 18 rxc input 20 rxer input 21 intrp input 22 txc input 23 txen input 24 txd0 input 25 txd1 input 26 txd2 input 27 txd3 input ddis ce tan to cable fault in meters ?? 0.38 register 1dh, bits[8:0] ?? ? =
? 2016 microchip technology inc. ds00002275a-page 31 ksz8091mnx/rnb 3.10.1 nand tree i/o testing use the following procedure to check for faults on the ks z8091mnx/rnb digital i/o pin connections to the board: 1. enable nand tree mode using either a hardware strap-in pin (nand_tree#, pin 21) or software (register 16h, bit [5]). 2. use board logic to drive all ksz8091m nx/rnb nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz8091mnx/rnb nand tree pin order, as follows: a) toggle the first pin (mdio) from high to low, and verify that the crs/config1 pin s witches from high to low to indicate that the firs t pin is connected properly. b) leave the first pin (mdio) low. c) toggle the second pin (mdc) from high to low, and verify that the crs/config1 pin switches from low to high to indicate that the second pin is connected properly. d) leave the first pin (mdio) and the second pin (mdc) low. e) toggle the third pin (rxd3/phyad0) from high to lo w, and verify that the crs/config1 pin switches from high to low to indicate that the third pin is connected properly. f) continue with this sequence until all ksz8091mnx /rnb nand tree input pins have been toggled. each ksz8091mnx/rnb nand tree input pin must cause the crs/config1 output pin to t oggle high-to-low or low- to-high to indicate a good connection. if the crs/config1 pin fails to toggle when the ksz8091mnx/rnb input pin toggles from high to low, the input pin has a fault. 3.11 power management the ksz8091mnx/rnb incorporates a number of power-management modes and features that pr ovide methods to consume less energy. these are discussed in the following sections. 30 led0 input 28 col input 29 crs output table 3-8: nand tree test pin order for ksz8091rnb pin number pin name nand tree description 11 mdio input 12 mdc input 15 rxd1 input 16 rxd0 input 18 crs_dv input 19 ref_clk input 20 rxer input 21 intrp input 22 pme_en input 23 txen input 24 txd0 input 25 txd1 input 30 led0 input 31 led1 input 28 config0 input 29 config1 output table 3-7: nand tree test pin order for ksz8091mnx (continued) pin number pin name nand tree description
ksz8091mnx/rnb ds00002275a-page 32 ? 2016 microchip technology inc. 3.11.1 power-saving mode power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a ?1? to register 1fh, bit [1 0], and is in effect when auto-negotiation mode is enabled and the cable is discon- nected (no link). in this mode, the ksz80 91mnx/rnb shuts down all transceiver blocks, ex cept for the transmitter, energy detect, and pll circuits. by default, power-saving mode is disabled after power-up. 3.11.2 energy-detect power-down mode energy-detect power-down (edpd) mode is used to furthe r reduce transceiver power consumption when the cable is unplugged. it is enabled by writing a ?0? to register 18h, bit [11], and is in effe ct when auto-negotiation mode is enabled and the cable is disconnected (no link). edpd mode works with the pll off (set by writing a ?1? to regi ster 10h, bit [4] to automatic ally turn the pll off in edpd mode) to turn off all ksz8091mnx/rnb transceiver blo cks except the transmitter and energy-detect circuits. power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres- ence of a link partner. the periodic transmission of link pulses is needed to ensure the ksz8091mnx/rnb and its link partner, when operating in the same low-power state and wit h auto mdi/mdi-x disabled, can wake up when the cable is connected between them. by default, energy-detect power-down mode is disabled after power-up. 3.11.3 power-down mode power-down mode is used to power down the ksz8091mnx/rnb device when it is not in use after power-up. it is enabled by writing a ?1? to register 0h, bit [11]. in this mode, the ksz8091mnx/rnb disables all internal functions except the mii management interface. the ksz8091mnx/rnb exits (disables) power-down mode afte r register 0h, bit [11] is set back to ?0?. 3.11.4 slow-oscillator mode slow-oscillator mode is used to disconnect the input refe rence crystal/clock on xi (pin 9) and select the on-chip slow oscillator when the ksz8091mnx/rnb device is not in use after power-up. it is enabled by writing a ?1? to register 11h, bit [5]. slow-oscillator mode works in conjunction with power-down mode to put the ksz8091mnx/rnb device in the lowest power state, with all internal functions disabled except the mii management interf ace. to properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow-oscillator mode by writing a ?0? to register 11h, bit [5]. 2. disable power-down mode by writing a ?0? to register 0h, bit [11]. 3. initiate software reset by writin g a ?1? to register 0h, bit [15].
? 2016 microchip technology inc. ds00002275a-page 33 ksz8091mnx/rnb 3.12 energy efficient ethernet (eee) the ksz8091mnx implements energy efficient ethernet ( eee) for the media independent interface (mii) as described in ieee standard 802.3az. the standard is defined around an eee-compliant mac on the host side and an eee-com- pliant link partner on the line side that supp ort special signaling associated wit h eee. eee saves power by keeping the ac signal on the copper ethernet cable at approximately 0v peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status. this is referred to as low-power idle (lpi) mode or state. similarly, the ksz8091rnb implements eee for the reduced media independent interface (rmii) as described in ieee standard 802.3az for line signaling by the two differential pairs (analog side) and according to the multi-source agree- ment (msa) of collaborating fast ethernet chip vendors for the rmii (digit al side). this agreement is based on the ieee standard?s eee implementation for mii (100 mbps). during lpi mode, the copper link responds automatically when it receives traffic and resumes normal phy operation immediately, without blockage of traffic or loss of packe t. this involves exiting lpi mode and returning to normal 100 mbps operating mode. wake-up time is <30 s for 100base-tx. the lpi state is controlled independently for transmit and receiv e paths, allowing the lpi state to be active (enabled) for: ? transmit cable path only ? receive cable path only ? both transmit and receive cable paths the ksz8091mnx/rnb has the eee function disabled as the power-up default setting. to enable the eee function for 100 mbps mode, use the following programming sequence: 1. enable 100 mbps eee mode advertisement by writing a ?1? to mmd address 7h, register 3ch, bit [1]. 2. restart auto-negotiation by writing a ?1? to standard register 0h, bit [9]. for standard (non-eee) 10base-t mode, normal link pulses (nlps) with long periods of no ac signal transmission are used to maintain the link during the idle period when there is no traffic activity. to save more power, the ksz8091mnx/ rnb provides the option to enable 10base-te mode, which sa ves additional power by reducing the transmitted signal amplitude from 2.5v to 1.75v. to enable 10base-te mode, write a ?1? to standard register 13h, bit [4]. during lpi mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. approxi- mately every 20 to 22 milliseconds, a refresh transmission of 20 0 to 220 microseconds is sent to the link partner. the refresh transmissions and quiet periods are shown in figure 3-10 . 3.12.1 transmit directio n control (mac-to-phy) the ksz8091mnx enters lpi mode for the transmit direct ion when its attached eee-compliant mii mac de-asserts txen, asserts txer, and sets txd[3:0] to 0001. the ksz 8091mnx remains in the lpi transmit state while the mac maintains the states of these signals. when the mac change s any of the txen, txer, or tx data signals from their lpi state values, the ksz8091mnx exits the lpi transmit state. the txc clock is not stopped, because it is sourced fr om the phy and is used by the mac for mii transmit. figure 3-11 shows the lpi transition for mii (100 mbps) transmit. figure 3-10: lpi mode (refresh transmissions and quiet periods) active data/ idle sleep refresh quiet quiet quiet refresh wake idle data/ idle low-power active ts tq tr tw_phy tw_system
ksz8091mnx/rnb ds00002275a-page 34 ? 2016 microchip technology inc. similarly, the ksz8091rnb enters lpi m ode for the transmit direction when its attached eee-compliant rmii mac de- asserts txen and sets txd [1:0] to 01. the ksz8091rnb re mains in the lpi transmit state while the rmii mac main- tains the states of these signals. when the rmii mac changes any of the txen or tx data signals from their lpi state values, the ksz8091rnb exits the lpi transmit state. figure 3-12 shows the lpi transition for rmii (100 mbps) transmit. 3.12.2 receive directio n control (phy-to-mac) the ksz8091mnx enters lpi mode for the receive direction wh en it receives the /p/ code bit pattern (sleep/refresh) from its eee-compliant link partner. it then de-asserts rxdv, asserts rxer, and drives rxd[3:0] to 0001. the ksz8091mnx remains in the lpi receive stat e while it continues to receive the refr esh from its link partner, so it will continue to maintain and drive the lpi output states fo r the mii receive signals to inform the attached eee-compliant mii mac that it is in the lpi receive state. when the ksz 8091mnx receives a non /p/ code bit pattern (non-refresh), it exits the lpi receive state and sets the rxdv, rxer, and rx data signals to set a normal frame or normal idle. the ksz8091mnx stops the rxc clock outpu t to the mac after nine or more rxc clock cycles have occurred in the lpi receive state, to save more power. by default, rxc clo ck stoppage is enabled. it is disabled by writing a ?0? to mmd address 3h, register 0h, bit [10]. figure 3-13 shows the lpi transition for mii (100 mbps) receive. figure 3-11: lpi transition - mii (100 mbps) transmit figure 3-12: lpi transition - rmii (100 mbps) transmit 0001 wake time enter low power state exit low power state txc txen txd[3:0] txer ref_clk txen txd[1:0] xx xx 00 00 01 01 data idle assert lpi idle preamble wake time
? 2016 microchip technology inc. ds00002275a-page 35 ksz8091mnx/rnb similarly, the ksz8091rnb enters lpi mode for the receive direction when it receives the /p/ code bit pattern (sleep/ refresh) from its eee-compliant link partner. it then de- asserts crs_dv and drives rx d[1:0] to 01. the ksz8091rnb remains in the lpi receive state while it continues to receive t he refresh from its link partner, so it will continue to mainta in and drive the lpi output states for the rmii receive signals to inform the attac hed eee-compliant rmii mac that it is in the lpi receive state. when the ksz8091rnb receives a non /p / code bit pattern (non-refresh), it exits the lpi receive state and sets the crs_dv and rx data signals to set a normal frame or normal idle. figure 3-14 shows the lpi transition for rmii (100 mbps) receive. 3.12.3 registers asso ciated with eee the following registers are provided for eee configuration and management: ? standard register 13h - afe control 4 (to enable 10base-te mode) ? mmd address 1h, register 0h - pm a/pmd control 1 (to enable lpi) ? mmd address 1h, register 1h - pm a/pmd status 1 (for lpi status) ? mmd address 3h, register 0h - eee pcs contro l 1 (to stop rxc clock for ksz8091mnx only) ? mmd address 7h, register 3ch - eee advertisement ? mmd address 7h, register 3dh - eee link partner advertisement figure 3-13: lpi transition - mii (100 mbps) receive figure 3-14: lpi transition - rmii (100 mbps) receive xx xx xx xx xx xx xx 0001 ? 9 cycles rxc rx_dv rxd[3:0] rxer enter low power state exit low power state ref_clk crs_dv rxd[1:0] xx xx 00 00 01 01 data idle assert lpi idle preamble
ksz8091mnx/rnb ds00002275a-page 36 ? 2016 microchip technology inc. 3.13 wake-on-lan wake-on-lan (wol) is normally a mac-bas ed function to wake up a host system (for ex ample, an et hernet end device, such as a pc) that is in stand by power mode. wake-up is triggered by receiving and detecting a special packet (commonly referred to as the ?magic packe t?) that is sent by the remote link partner. the ksz8091mnx/rnb can per- form the same wol function if the mac address of its associated mac device is enter ed into the ksz8091mnx/rnb phy registers for magic-packet detection. when the ksz8 091mnx/rnb detects the magic packet, it wakes up the host by driving its power management event (pme) output pin low. by default, the wol function is disabled. it is enabled by setting the enabling bit and config uring the associated registers for the selected pme wake-up detection method. the ksz8091mnx/rnb provides three methods to trigger a pme wake-up: ? magic-packet detection ?customized-pa cket detection ? link status change detection 3.13.1 magic-packet detection the magic packet?s frame format starts with 6 bytes of 0xff h and is followed by 16 repetitions of the mac address of its associated mac device (local mac device). when the magic packet is detected from its link pa rtner, the ksz8091mnx/rnb asse rts its pme output pin low. the following mmd address 1fh registers are provided for magic-packet detection: ? magic-packet detection is enabled by writing a ?1? to mmd address 1fh, register 0h, bit [6] ? the mac address (for the local mac device) is written to and stored in mmd address 1fh, registers 19h ? 1bh the ksz8091mnx/rnb does not generate the magic packet. th e magic packet must be provided by the external sys- tem. 3.13.2 customized-packet detection the customized packet has associated regi ster/bit masks to sele ct which byte, or bytes, of the first 64 bytes of the packet to use in the crc calculation. after the ksz8091mnx/rnb rece ives the packet from its link partner, the selected bytes for the received packet are used to calculate the crc. the calculated crc is compar ed to the expected crc value that was previously written to and stored in the ksz8091mnx/rnb phy re gisters. if there is a match, the ksz8091mnx/rnb asserts its pme output pin low. four customized packets are provided to support four types of wake-up scenarios. a dedicated set of registers is used to configure and enable each customized packet. the following mmd registers are provided for customized-packet detection: ? each of the four customized packets is enabled via mmd address 1fh, register 0h, - bit [2] // for custom ized packets, type 0 - bit [3] // for custom ized packets, type 1 - bit [4] // for custom ized packets, type 2 - bit [5] // for custom ized packets, type 3 ? masks to indicate which of the first 64-byte s to use in the crc calculation are set in: - mmd address 1fh, registers 1h ? 4h // for customized packets, type 0 - mmd address 1fh, registers 7h ? ah // for customized packets, type 1 - mmd address 1fh, registers dh ? 10h // for customized packets, type 2 - mmd address 1fh, registers 13h ? 16h // for customized packets, type 3 ? 32-bit expected crcs are written to and stored in: - mmd address 1fh, registers 5h ? 6h // for customized packets, type 0 - mmd address 1fh, registers bh ? ch // for customized packets, type 1 - mmd address 1fh, registers 11h ? 12h // for customized packets, type 2 - mmd address 1fh, registers 17h ? 18h // for customized packets, type 3
? 2016 microchip technology inc. ds00002275a-page 37 ksz8091mnx/rnb 3.13.3 link status change detection if link status change detection is enabled, the ksz8091mnx /rnb asserts its pme output pin low whenever there is a link status change, using the following mmd address 1fh regist er bits and their enabled (1) or disabled (0) settings: ? mmd address 1fh, register 0h, bit [0] // for link-up detection ? mmd address 1fh, register 0h, bit [1] // for link-down detection the pme output signal is available on either intrp/pme_n2 (pin 21) or led0/pme_n1 (pin 30), and is enabled using standard register 16h, bit [15]. mmd addre ss 1fh, register 0h, bits [15:14] defin es and selects the output functions for pins 21 and 30. the pme output is active low and requires a 1 k ? pull-up to the v ddio supply. when asserted, the pme output is cleared by disabling the register bit that e nabled the pme trigger source (magic packet, customized packet, link status change). 3.14 reference circuit for power and ground connections the ksz8091mnx/rnb is a single 3.3v supply device with a built -in regulator to supply the 1.2v core. the power and ground connections are shown in figure 3-15 and table 3-9 for 3.3v v ddio . figure 3-15: ksz8091mnx/rnb power and ground connections table 3-9: ksz8091mnx/rnb power pin description power pin pin number description vdd_1.2 2 decouple with 2.2 f and 0.1 f capacitors to ground. vdda_3.3 3 connect to board?s 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 17 connect to board?s 3.3v supply for 3.3v v ddio . decouple with 22 f and 0.1 f capacitors to ground. vddio ksz8091mnx/rnb gnd 3.3v vdda_3.3 0.1f 2 vdd_1.2 3 ferrite bead 17 1 paddle 2.2f 0.1f 22f 0.1f 22f
ksz8091mnx/rnb ds00002275a-page 38 ? 2016 microchip technology inc. 3.15 typical current/power consumption table 3-10 , ta b l e 3 - 11 , and ta b l e 3 - 1 2 show typical values for current consum ption by the transceiver (vdda_3.3) and digital i/o (vddio) power pins, and typical values for po wer consumption by the ksz8091mnx/rnb device for the indi- cated nominal operating voltages. these current and power c onsumption values include the transmit driver current and on-chip regulator current for the 1.2v core. table 3-10: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power 100base-tx link-up (no traffic) 34 ma 12 ma 152 mw 100base-tx full-duplex @ 100% utilization 34 ma 13 ma 155 mw 10base-t link-up (no traffic) 14 ma 11 ma 82.5 mw 10base-t full-duplex @ 100% utilization 30 ma 11 ma 135 mw eee 100 mbps link-up mode (transmit and receive in lpi state with no traffic) 13 ma 10 ma 75.9 mw power-saving mode (reg. 1fh, bit [10] = 1) 13 ma 10 ma 75.9 mw edpd mode (reg. 18h, bit [11] = 0) 10 ma 10 ma 66 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 ma 1.54 ma 17.5 mw software power-down mode (reg. 0h, bit [11] =1) 2.59 ma 1.51 ma 13.5 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.36 ma 0.45 ma 5.97 mw table 3-11: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) total chip power 100base-tx link-up (no tr affic) 34 ma 11 ma 140 mw 100base-tx full-duplex @ 100% utilization 34 ma 12 ma 142 mw 10base-t link-up (no traffic) 15 ma 10 ma 74.5 mw 10base-t full-duplex @ 100% utilization 27 ma 10 ma 114 mw eee 100 mbps link-up mode (transmit and receive in lpi state with no traffic) 13 ma 10 ma 67.9 mw power-saving mode (reg. 1fh, bit [10] = 1) 13 ma 10 ma 67.9 mw edpd mode (reg. 18h, bit [11] = 0) 11 ma 10 ma 61.3 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.55 ma 1.35 ma 15.1 mw software power-down mode (reg. 0h, bit [11] =1) 2.29 ma 1.34 ma 10.9 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.15 ma 0.29 ma 4.52 mw table 3-12: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os (vddio) total chip power 100base-tx link-up (no tr affic) 34 ma 11 ma 132 mw 100base-tx full-duplex @ 100% utilization 34 ma 12 ma 134 mw 10base-t link-up (no traffic) 15 ma 9 ma 65.7 mw 10base-t full-duplex @ 100% utilization 27 ma 9 ma 105 mw
? 2016 microchip technology inc. ds00002275a-page 39 ksz8091mnx/rnb eee 100 mbps link-up mode (transmit and receive in lpi state with no traffic) 13 ma 9 ma 59.1 mw power-saving mode (reg. 1fh, bit [10] = 1) 13 ma 9 ma 59.1 mw edpd mode (reg. 18h, bit [11] = 0) 11 ma 9 ma 52.5 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 ma 1.21 ma 15.5 mw software power-down mode (reg. 0h, bit [11] =1) 2.79 ma 1.21 ma 11.4 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.65 ma 0.19 ma 5.79 mw table 3-12: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os (vddio) total chip power
ksz8091mnx/rnb ds00002275a-page 40 ? 2016 microchip technology inc. 4.0 register descriptions the register space within the ksz8091mnx/rnb consists of two distinct areas. ? standard registers // direct register access ? mdio manageable device (mmd) registers // indirect register access the ksz8091mnx/rnb supports the following standard registers. 4.1 register map table 4-1: standard registers supported by ksz8091mnx/rnb register number (hex) description ieee defined registers 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h auto-negotiation link partner next page ability 9h - ch reserved dh mmd access - control eh mmd access - register/data fh reserved vendor specific registers 10h digital reserved control 11h afe control 1 12h reserved 13h afe control 4 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h - 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd cable diagnostic 1eh phy control 1 1fh phy control 2
? 2016 microchip technology inc. ds00002275a-page 41 ksz8091mnx/rnb the ksz8091mnx/rnb supports the following mmd device addres ses and their associated r egister addresses, which make up the indirect mmd registers. table 4-2: mmd registers su pported by ksz8091mnx/rnb device address (hex) register address (hex) description 1h 0h pma/pmd control 1 1h pma/pmd status 1 3h 0h eee pcs control 1 7h 3ch eee advertisement 3dh eee link partner advertisement 1fh 0h wake-on-lan ? control 1h wake-on-lan ? customized packet, type 0, mask 0 2h wake-on-lan ? customized packet, type 0, mask 1 3h wake-on-lan ? customized packet, type 0, mask 2 4h wake-on-lan ? customized packet, type 0, mask 3 5h wake-on-lan ? customized packet, type 0, expected crc 0 6h wake-on-lan ? customized packet, type 0, expected crc 1 7h wake-on-lan ? customized packet, type 1, mask 0 8h wake-on-lan ? customized packet, type 1, mask 1 9h wake-on-lan ? customized packet, type 1, mask 2 ah wake-on-lan ? customized packet, type 1, mask 3 bh wake-on-lan ? customized packet, type 1, expected crc 0 ch wake-on-lan ? customized packet, type 1, expected crc 1 dh wake-on-lan ? customized packet, type 2, mask 0 eh wake-on-lan ? customized packet, type 2, mask 1 fh wake-on-lan ? customized packet, type 2, mask 2 10h wake-on-lan ? customized packet, type 2, mask 3 11h wake-on-lan ? customized packet, type 2, expected crc 0 12h wake-on-lan ? customized packet, type 2, expected crc 1 13h wake-on-lan ? customized packet, type 3, mask 0 14h wake-on-lan ? customized packet, type 3, mask 1 15h wake-on-lan ? customized packet, type 3, mask 2 16h wake-on-lan ? customized packet, type 3, mask 3 17h wake-on-lan ? customized packet, type 3, expected crc 0 18h wake-on-lan ? customized packet, type 3, expected crc 1 19h wake-on-lan ? magic packet, mac-da-0 1ah wake-on-lan ? magic packet, mac-da-1 1bh wake-on-lan ? magic packet, mac-da-2
ksz8091mnx/rnb ds00002275a-page 42 ? 2016 microchip technology inc. 4.2 standard registers standard registers provide direct read/writ e access to a 32-register address space, as defined in clause 22 of the ieee 802.3 specification. within this address space, the first 16 registers (registers 0h to fh) are defined according to the ieee specification, while the remaining 16 registers (registers 10h to 1fh) are defined specific to the phy vendor. table 4-3: ieee defined register descriptions address name description mode note 4-1 default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loopback 1 = loopback mode 0 = normal operation rw 0 0.13 speed select 1 = 100 mbps 0 = 10 mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by the speed strapping pin (ksz8091rnb only). see the strap-in options - ksz8091rnb section for details. 0.12 auto-negoti- ation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, the auto-negotiation result overrides the settings in registers 0.13 and 0.8. rw set by the nwayen strapping pin. see the strap-in options - ksz8091mnx sec- tion for details. 0.11 power-down 1 = power-down mode 0 = normal operation if software reset (register 0.15) is used to exit power-down mode (register 0.11 = 1), two soft- ware reset writes (register 0.15 = 1) are required. the first write clears power-down mode; the sec- ond write resets the chip and re-latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw set by the iso strap- ping pin. see the strap-in options - ksz8091mnx sec- tion for details. 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw the inverse of the duplex strapping pin value. see the strap-in options - ksz8091mnx sec- tion for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved reserved ro 000_0000
? 2016 microchip technology inc. ds00002275a-page 43 ksz8091mnx/rnb register 1h - basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full-duplex 1 = capable of 100 mbps full-duplex 0 = not capable of 100 mbps full-duplex ro 1 1.13 100base-tx half-duplex 1 = capable of 100 mbps half-duplex 0 = not capable of 100 mbps half-duplex ro 1 1.12 10base-t full-duplex 1 = capable of 10 mbps full-duplex 0 = not capable of 10 mbps full-duplex ro 1 1.11 10base-t half-duplex 1 = capable of 10 mbps half-duplex 0 = not capable of 10 mbps half-duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto-negoti- ation com- plete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto-negoti- ation ability 1 = can perform auto-negotiation 0 = cannot perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h - phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organi- zationally unique identif ier (oui). kendin com- munication?s oui is 0010a1 (hex). ro 0022h register 3h - phy identifier 2 3.15:10 phy id num- ber assigned to the 19th through 24th bits of the orga- nizationally unique iden tifier (oui). kendin com- munication?s oui is 0010a1 (hex). ro 0001_01 3.9:4 model num- ber six-bit manufacturer?s model number ro 01_0110 3.3:0 revision number four-bit manufacturer?s revision number ro indicates silicon revision. register 4h - auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability rw 1 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 table 4-3: ieee defined regist er descriptions (continued) address name description mode note 4-1 default
ksz8091mnx/rnb ds00002275a-page 44 ? 2016 microchip technology inc. 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability rw set by the speed strapping pin (ksz8091rnb only). see the strap-in options - ksz8091rnb section for details. 4.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability rw set by the speed strapping pin (ksz8091rnb only). see the strap-in options - ksz8091rnb section for details. 4.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h - auto-negotia tion link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause ro 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability ro 0 5.4:0 selector field [00001] = 802.3 after an completes. ro 0_0000 table 4-3: ieee defined regist er descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002275a-page 45 ksz8091mnx/rnb register 6h - auto-n egotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capabil- ity ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto-negoti- ation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7h - auto-n egotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowl- edge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h - link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful re ceipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowl- edge2 1 = can act on the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = previous value of transmitted link code word equal to logic 1 ro 0 8.10:0 message field 11-bit wide field to encode 2048 messages ro 000_0000_0000 table 4-3: ieee defined regist er descriptions (continued) address name description mode note 4-1 default
ksz8091mnx/rnb ds00002275a-page 46 ? 2016 microchip technology inc. note 4-1 rw = read/write; ro = read only; sc = self-cleared; lh = latch high; ll = latch low. register dh - mmd access - control d.15:14 mmd ? operation mode for the selected mmd device address (bits [4:0] of this register), these two bits select one of the fol- lowing register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address these five bits set the mmd device address. rw 0_0000 register eh - mmd access - register/data e.15:0 mmd ? register/ data for the selected mmd device address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register con- tains the read/write register address for the mmd device address. otherwise, this register contains the read/write data value for the mmd device address and its selected register address. see also reg. dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. rw 0000_0000_0000_ 0000 table 4-4: vendor specific register descriptions address name description mode note 4-1 default register 10h ? digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll off 1 = turn pll off automatically in edpd mode 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode rw 0 10.3:0 reserved reserved rw 0000 register 11h ? afe control 1 11.15:6 reserved reserved rw 0000_0000_00 11.5 slow-oscilla- tor mode enable slow-oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on-chip slow oscillator when the ksz8091mnx/rnb device is not in use after power-up. 1 = enable 0 = disable this bit automatically sets software power-down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 table 4-3: ieee defined regist er descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002275a-page 47 ksz8091mnx/rnb register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 16h ? operation mode strap override 16.15 pme enable pme for wake-on-lan 1 = enable 0 = disable this bit works in conjunction with mmd address 1fh, reg. 0h, bits [15:14] to define the output for pins 21 and 30. rw set by the pme_en strapping pin. see the strap-in options - ksz8091mnx sec- tion for details. 16.14:11 reserved reserved rw 000_0 16.10 reserved reserved ro 0 16.9 b- cast_off override 1 = override strap-in for b-cast_off if bit is ?1?, phy address 0 is non-broadcast. rw 0 16.8 reserved reserved rw 0 16.7 mii b-to-b override 1 = override strap-in for mii back-to-back mode (also set bit 0 of this register to ?1?) this bit applies only to ksz8091mnx. rw 0 16.6 rmii b-to-b override 1 = override strap-in for rmii back-to-back mode (also set bit 1 of this register to ?1?) this bit applies only to ksz8091rnb. rw 0 16.5 nand tree override 1 = override strap-in for nand tree mode rw 0 16.4:2 reserved reserved rw 0_00 16.1 rmii override 1 = override strap-in for rmii mode this bit applies only to ksz8091rnb. rw 0 16.0 mii override 1 = override strap-in for mii mode this bit applies only to ksz8091mnx. rw 1 register 17h - operation mode strap status 17.15:13 phyad[2:0] strap-in sta- tus [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = strap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro ? 17.12:10 reserved reserved ro ? 17.9 b- cast_off strap-in status 1 = strap to b-cast_off if bit is ?1?, phy address 0 is non-broadcast. ro ? 17.8 reserved reserved ro ? 17.7 mii b-to-b strap-in status 1 = strap to mii back-to-back mode this bit applies only to ksz8091mnx. ro ? 17.6 rmii b-to-b strap-in status 1 = strap to rmii back-to-back mode this bit applies only to ksz8091rnb. ro ? table 4-4: vendor specific regi ster descriptions (continued) address name description mode note 4-1 default
ksz8091mnx/rnb ds00002275a-page 48 ? 2016 microchip technology inc. 17.5 nand tree strap-in status 1 = strap to nand tree mode ro ? 17.4:2 reserved reserved ro ? 17.1 rmii strap-in status 1 = strap to rmii mode this bit applies only to ksz8091rnb. ro ? 17.0 mii strap-in status 1 = strap to mii mode this bit applies only to ksz8091mnx. ro ? register 18h - expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy-detect power-down mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10 100base-tx latency 1 = mii output is random latency 0 = mii output is fixed latency for both settings, all bytes of received preamble are passed to the mii output. this bit applies only to the ksz8091mnx. rw 0 18.9:7 reserved reserved rw 00_0 18.6 10base-t preamble restore 1 = restore received preamble to mii output 0 = remove all seven bytes of preamble before sending frame (starting with sfd) to mii output this bit applies only to the ksz8091mnx. rw 0 18.5:0 reserved reserved rw 00_0001 register 1bh ? interrupt control/status 1b.15 jabber inter- rupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error inter- rupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowl- edge inter- rupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link-down interrupt enable 1= enable link-down interrupt 0 = disable link-down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 table 4-4: vendor specific regi ster descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002275a-page 49 ksz8091mnx/rnb 1b.8 link-up interrupt enable 1 = enable link-up interrupt 0 = disable link-up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowl- edge inter- rupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link-down interrupt 1 = link-down occurred 0 = link-down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link-up interrupt 1 = link-up occurred 0 = link-up did not occur ro/sc 0 register 1dh ? linkmd control/status 1d.15 cable diag- nostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diag- nostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh ? phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro ? 1e.6 reserved reserved ro 0 table 4-4: vendor specific regi ster descriptions (continued) address name description mode note 4-1 default
ksz8091mnx/rnb ds00002275a-page 50 ? 2016 microchip technology inc. 1e.5 mdi/mdi-x state 1 = mdi-x 0 = mdi ro ? 1e.4 energy detect 1 = signal present on receive differential pair 0 = no signal detected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indication [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base- tx half-duplex [011] = reserved [100] = reserved [101] = 10base-t full-duplex [110] = 100base- tx full-duplex [111] = reserved ro 000 register 1fh ? phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = microchip auto mdi/mdi-x mode rw 1 1f.14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 1 = mdi-x mode transmit on rxp, rxm (pins 5, 4) and receive on txp, txm (pins 7, 6) 0 = mdi mode transmit on txp, txm (pins 7, 6) and receive on rxp, rxm (pins 5, 4) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 rmii refer- ence clock select 1 = rmii 50 mhz clock mode; clock input to xi (pin 9) is 50 mhz 0 = rmii 25 mhz clock mode; clock input to xi (pin 9) is 25 mhz this bit applies only to ksz8091rnb. rw 0 1f.6 reserved reserved rw 0 1f.5:4 led mode [00] = led1: speed led0: link/activity [01] = led1: activity led0: link [10], [11] = reserved the led1 pin applies only to the ksz8091rnb. rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 table 4-4: vendor specific regi ster descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002275a-page 51 ksz8091mnx/rnb note 4-1 rw = read/write; ro = read only; sc = self-cleared. 4.3 mmd registers mmd registers provide indirect read/write access to up to 32 mmd device addresses with each device supporting up to 65,536 16-bit registers, as defined in clause 22 of the ieee 802.3 specification. the ksz8091mnx/rnb, however, uses only a small fraction of t he available registers. see the register descriptions section for a list of supported mmd device addresses and their associated register addresses. the following two standard registers serve as the porta l registers to access the indirect mmd registers. ? standard register dh ? mmd access ? control ? standard register eh ? mmd access ? register/data examples: mmd register write write mmd ? device address 1fh, register 0h = 0001h to enable link-up detection to trigger pme for wol. 1f.2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 enable sqe te s t 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 table 4-5: portal registers (acc ess to indirect mmd registers) address name description mode default register dh - mmd access - control d.15:14 mmd ? operation mode for the selected mmd device address (bits [4:0] of this register), these two bits select one of the fol- lowing register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address these five bits set the mmd device address. rw 0_0000 register eh - mmd access - register/data e.15:0 mmd ? register/ data for the selected mmd de vice address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register con- tains the read/write register address for the mmd device address. otherwise, this register contains the read/write data value for the mmd device address and its selected register address. see also reg. dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. rw 0000_0000_0000_ 0000 table 4-4: vendor specific regi ster descriptions (continued) address name description mode note 4-1 default
ksz8091mnx/rnb ds00002275a-page 52 ? 2016 microchip technology inc. 1. write register dh with 001fh // set up register address for mmd ? device address 1fh. 2. write register eh with 0000h // select register 0h of mmd ? device address 1fh. 3. write register dh with 401fh // select register data for mmd ? device address 1fh, register 0h. 4. write register eh with 0001h // write value 0001h to mmd ? device address 1fh, register 0h. mmd register read read mmd ? device address 1fh, register 19h ? 1bh for the magic packet?s mac address 1. write register dh with 001fh // set up register address for mmd ? device address 1fh. 2. write register eh with 0019h // select register 19h of mmd ? device address 1fh. 3. write register dh with 801fh // select register data for mmd ? device address 1fh, register 19h // with post increments 4. read register eh // read data in mmd ? device address 1fh, register 19h. 5. read register eh // read data in mmd ? device address 1fh, register 1ah. 6. read register eh // read data in mmd ? device address 1fh, register 1bh. table 4-6: mmd register descriptions address name description mode default mmd address 1h, register 0h ? pma/pmd control 1 1.0.15:13 reserved reserved rw 000 1.0.12 lpi enable lower power idle enable rw 0 1.0.11:0 reserved reserved rw 0000_0000_0000 mmd address 1h, register 1h ? pma/pmd status 1 1.1.15:9 reserved reserved ro 0000_000 1.1.8 lpi state entered 1 = pma/pmd has entered lpi state 0 = pma/pmd has not entered lpi state ro/lh 0 1.1.7:4 reserved reserved ro 0000 1.1.3 lpi state indication 1 = pma/pmd is currently in lpi state 0 = pma/pmd is currently not in lpi state ro 0 1.1.2:0 reserved reserved ro 000 mmd address 3h, register 0h ? eee pcs control 1 3.0.15:12 reserved reserved ro 0000 3.0.11 reserved reserved rw 1 3.0.10 100base-tx rxc clock stoppable during receive lower-power idle mode, 1 = rxc clock is stoppable for 100base-tx 0 = rxc clock is not stoppable for 100base-tx this bit applies only to ksz8091mnx. rw 1 3.0.9:4 reserved reserved rw 00_0001 3.0.3:2 reserved reserved ro 00 3.0.1:0 reserved reserved rw 00 mmd address 7h, register 3ch ? eee advertisement 7.3c.15:3 reserved reserved ro 0000_0000_0000_0 7.3c.2 1000base-t eee capable 0 = 1000 mbps eee is not supported ro 0 7.3c.1 100base-tx eee capable 1 = 100 mbps eee capable 0 = no 100 mbps eee capability this bit is set to ?0? as the default after power-up or reset. set this bit to ?1? to enable 100 mbps eee mode. rw 0 7.3c.0 reserved reserved ro 0 mmd address 7h, register 3dh ? eee link partner advertisement 7.3d.15:3 reserved reserved ro 0000_0000_0000_0
? 2016 microchip technology inc. ds00002275a-page 53 ksz8091mnx/rnb 7.3d.2 1000base-t eee capable 1 = 1000 mbps eee capable 0 = no 1000 mb ps eee capability ro 0 7.3d.1 100base-tx eee capable 1 = 100 mbps eee capable 0 = no 100 mbps eee capability ro 0 7.3d.0 reserved reserved ro 0 mmd address 1fh, register 0h ? wake-on-lan ? control 1f.0.15:14 pme output select these two bits work in conjunction with reg. 16h, bit [15] for pme enable to define the output for pins 21 and 30. intrp/pme_n2 (pin 21) 00 = intrp output 01 = pme_n2 output 10 = intrp and pme_n2 output 11 = reserved led0/pme_n1 (pin 30) 00 = pme_n1 output 01 = led0 output 10 = led0 output 11 = pme_n1 output rw 00 1f.0.13:7 reserved reserved ro 00_0000_0 1f.0.6 magic packet detect enable 1 = enable magic-packet detection 0 = disable magic-packet detection rw 0 1f.0.5 custom- packet type 3 detect enable 1 = enable custom-packet, type 3 detection 0 = disable custom-packet, type 3 detection rw 0 1f.0.4 custom- packet type 2 detect enable 1 = enable custom-packet, type 2 detection 0 = disable custom-packet, type 2 detection rw 0 1f.0.3 custom- packet type 1 detect enable 1 = enable custom-packet, type 1 detection 0 = disable custom-packet, type 1 detection rw 0 1f.0.2 custom- packet type 0 detect enable 1 = enable custom-packet, type 0 detection 0 = disable custom-packet, type 0 detection rw 0 1f.0.1 link-down detect enable 1 = enable link-down detection 0 = disable link-down detection rw 0 1f.0.0 link-up detect enable 1 = enable link-up detection 0 = disable link-up detection rw 0 table 4-6: mmd register d escriptions (continued) address name description mode default
ksz8091mnx/rnb ds00002275a-page 54 ? 2016 microchip technology inc. mmd address 1fh, register 1h ? wake-on-lan ? customized packet, type 0, mask 0 mmd address 1fh, register 7h ? wake-on-lan ? customized packet, type 1, mask 0 mmd address 1fh, register dh ? wake-on-lan ? customized packet, type 2, mask 0 mmd address 1fh, register 13h ? wake-on-lan ? customized packet, type 3, mask 0 1f.1.15:0 1f.7.15:0 1f.d.15:0 1f.13.15:0 custom packet type x mask 0 this register selects the bytes in the first 16 bytes of the packet (bytes 1 thru 16) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte-16 ... : ... bit [1]: byte-2 bit [0]: byte-1 rw 0000_0000_0000_ 0000 mmd address 1fh, register 2h ? wake-on-lan ? customized packet, type 0, mask 1 mmd address 1fh, register 8h ? wake-on-lan ? customized packet, type 1, mask 1 mmd address 1fh, register eh ? wake-on-lan ? customized packet, type 2, mask 1 mmd address 1fh, register 14h ? wake-on-lan ? customized packet, type 3, mask 1 1f.2.15:0 1f.8.15:0 1f.e.15:0 1f.14.15:0 custom packet type x mask 1 this register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte-32 ... : ... bit [1]: byte-18 bit [0]: byte-17 rw 0000_0000_0000_ 0000 mmd address 1fh, register 3h ? wake-on-lan ? customized packet, type 0, mask 2 mmd address 1fh, register 9h ? wake-on-lan ? customized packet, type 1, mask 2 mmd address 1fh, register fh ? wake-on-lan ? customized packet, type 2, mask 2 mmd address 1fh, register 15h ? wake-on-lan ? customized packet, type 3, mask 2 1f.3.15:0 1f.9.15:0 1f.f.15:0 1f.15.15:0 custom packet type x mask 2 this register selects the bytes in the third 16 bytes of the packet (bytes 33 thru 48) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte-48 ... : ... bit [1]: byte-34 bit [0]: byte-33 rw 0000_0000_0000_ 0000 table 4-6: mmd register d escriptions (continued) address name description mode default
? 2016 microchip technology inc. ds00002275a-page 55 ksz8091mnx/rnb mmd address 1fh, register 4h ? wake-on-lan ? customized packet, type 0, mask 3 mmd address 1fh, register ah ? wake-on-lan ? customized packet, type 1, mask 3 mmd address 1fh, register 10h ? wake-on-lan ? customized packet, type 2, mask 3 mmd address 1fh, register 16h ? wake-on-lan ? customized packet, type 3, mask 3 1f.4.15:0 1f.a.15:0 1f.10.15:0 1f.16.15:0 custom packet type x mask 3 this register selects the bytes in the fourth 16 bytes of the packet (bytes 49 thru 64) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte-64 ... : ... bit [1]: byte-50 bit [0]: byte-49 rw 0000_0000_0000_ 0000 mmd address 1fh, register 5h ? wake-on-lan ? customized packet, type 0, expected crc 0 mmd address 1fh, register bh ? wake-on-lan ? customized packet, type 1, expected crc 0 mmd address 1fh, register 11h ? wake-on-lan ? customized packet, type 2, expected crc 0 mmd address 1fh, register 17h ? wake-on-lan ? customized packet, type 3, expected crc 0 1f.5.15:0 1f.b.15:0 1f.11.15:0 1f.17.15:0 custom packet type x crc 0 this register stores the lower two bytes for the expected crc. bit [15:8] = byte 2 (crc [15:8]) bit [7:0] = byte 1 (crc [7:0]) the upper two bytes for the expected crc are stored in the following register. rw 0000_0000_0000_ 0000 mmd address 1fh, register 6h ? wake-on-lan ? customized packet, type 0, expected crc 1 mmd address 1fh, register ch ? wake-on-lan ? customized packet, type 1, expected crc 1 mmd address 1fh, register 12h ? wake-on-lan ? customized packet, type 2, expected crc 1 mmd address 1fh, register 18h ? wake-on-lan ? customized packet, type 3, expected crc 1 1f.6.15:0 1f.c.15:0 1f.12.15:0 1f.18.15:0 custom packet type x crc 1 this register stores the upper two bytes for the expected crc. bit [15:8] = byte 4 (crc [31:24]) bit [7:0] = byte 3 (crc [23:16]) the lower two bytes for the expected crc are stored in the previous register. rw 0000_0000_0000_ 0000 mmd address 1fh, register 19h ? wake-on-lan ? magic packet, mac-da-0 1f.19.15:0 magic packet mac-da-0 this register stores the lower two bytes of the des- tination mac address for the magic packet. bit [15:8] = byte 2 (mac address [15:8]) bit [7:0] = byte 1 (mac address [7:0]) the upper four bytes of the destination mac address are stored in the following two registers. rw 0000_0000_0000_ 0000 mmd address 1fh, register 1ah ? wake-on-lan ? magic packet, mac-da-1 1f.1a.15:0 magic packet mac-da-1 this register stores the middle two bytes of the destination mac address for the magic packet. bit [15:8] = byte 4 (mac address [31:24]) bit [7:0] = byte 3 (mac address [23:16]) the lower two bytes and upper two bytes of the destination mac address are stored in the previous and following registers, respectively. rw 0000_0000_0000_ 0000 table 4-6: mmd register d escriptions (continued) address name description mode default
ksz8091mnx/rnb ds00002275a-page 56 ? 2016 microchip technology inc. note 4-1 rw = read/write; ro = read only; lh = latch high. mmd address 1fh, register 1bh ? wake-on-lan ? magic packet, mac-da-2 1f.1b.15:0 magic packet mac-da-2 this register stores the upper two bytes of the des- tination mac address for the magic packet. bit [15:8] = byte 6 (mac address [47:40]) bit [7:0] = byte 5 (mac address [39:32]) the lower four bytes of the destination mac address are stored in the previous two registers. rw 0000_0000_0000_ 0000 table 4-6: mmd register d escriptions (continued) address name description mode default
? 2016 microchip technology inc. ds00002275a-page 57 ksz8091mnx/rnb 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (v in ) (v dd_1.2 ).............................................................................................................................. ...................... ?0.5v to +1.8v (v ddio , v dda_3.3 ) .............................................................................................................................. ........ ?0.5v to +5.0v input voltage (all inputs)..................................................................................................... ....................... ?0.5v to +5.0v output voltage (all outputs)................................................................................................... .................... ?0.5v to +5.0v lead temperature (soldering, 10s) .............................................................................................. ......................... +260c storage temperature (t s ) .............. .............. .............. .............. .............. .............. .............. .............. ...... ?55c to +150c *exceeding the absolute maximum rating may damage the dev ice. stresses greater than the absolute maximum rating may cause permanent damage to the device. operation of the de vice at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 5.2 operating ratings** supply voltage (v ddio_3.3 , v dda_3.3 ) ........................................................................................................................ +3.135 v to +3.465v (v ddio_2.5 ) .............................................................................................................................. .......... +2.375v to +2.625v (v ddio_1.8 ) .............................................................................................................................. .......... +1.710v to +1.890v ambient temperature (t a commercial)................................................................................................................... ........................ 0c to +70c (t a industrial) ........... .............. .............. .............. .............. .............. .............. ........... ......... ........................ ?40c to +85c maximum junction temperature (t j max.) ........................................................................................................... +125c thermal resistance ( ja ).............................................................................................................................. +45.87c/w thermal resistance ( jc ) .............................................................................................................................+ 15.85c/w **the device is not guaranteed to function outside its operating ratings. note: do not drive input signals without power supplied to the device.
ksz8091mnx/rnb ds00002275a-page 58 ? 2016 microchip technology inc. 6.0 electrical characteristics t a = 25c. specification is for packaged product only. table 6-1: electrical characteristics parameters symbol min. typ. max. units note supply current (v ddio , v dda_3.3 = 3.3v), note 6-1 10base-t i dd1_3.3v ? 41 ? ma full-duplex traffic @ 100% utilization 100base-tx i dd2_3.3v ? 47 ? ma full-duplex traffic @ 100% utilization eee (100 mbps) mode i dd3_3.3v ?23?ma tx and rx paths in lpi state with no traffic edpd mode i dd4_3.3v ?20?ma ethernet cable disconnected (reg. 18h.11 = 0) power-down mode i dd5_3.3v ?4?ma software power-down (reg. 0h.11 = 1) cmos level inputs input high voltage v ih 2.0 ? ? v v ddio = 3.3v 1.8 ? ? v v ddio = 2.5v 1.3 ? ? v v ddio = 1.8v input low voltage v il ??0.8v v ddio = 3.3v ??0.7v v ddio = 2.5v ??0.5v v ddio = 1.8v input current |i in |??10a v in = gnd ~ v ddio cmos level outputs output high voltage v oh 2.4 ? ? v v ddio = 3.3v 2.0 ? ? v v ddio = 2.5v 1.5 ? ? v v ddio = 1.8v output low voltage v ol ??0.4v v ddio = 3.3v ??0.4v v ddio = 2.5v ??0.3v v ddio = 1.8v output tri-state leakage |i oz |??10a ? led output output drive current i led ? 8 ? ma each led pin (led0, led1) all pull-up/pull-down pins (including strap-in pins) internal pull-up resistance pu 30 45 73 k ? v ddio = 3.3v 39 61 102 k ? v ddio = 2.5v 48 99 178 k ? v ddio = 1.8v internal pull-down resistance pd 26 43 79 k ? v ddio = 3.3v 34 59 113 k ? v ddio = 2.5v 53 99 200 k ? v ddio = 1.8v 100base-tx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 0.95 ? 1.05 v 100 ? termination across differential output output voltage imbalance v imb ?? 2 % 100 ? termination across differential output rise/fall time t r /t f 3?5ns ? rise/fall time imbalance ? 0 ? 0.5 ns ? duty cycle distortion ? ? ? 0.25 ns ? overshoot ? ? ? 5 % ?
? 2016 microchip technology inc. ds00002275a-page 59 ksz8091mnx/rnb note 6-1 current consumption is for the single 3.3v supp ly ksz8091mnx/rnb device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz8091mnx/ rnb. output jitter ? ? 0.7 ? ns peak-to-peak 10base-t transmit (measured differentially after 1:1 transformer) peak differential output voltage v p 2.2 ? 2.8 v 100 ? termination across differential output jitter added ? ? ? 3.5 ns peak-to-peak rise/fall time t r /t f ?25?ns ? 10base-t receive squelch threshold v sq ? 400 ? mv 5 mhz square wave transmitter - drive setting reference voltage of i set v set ?0.65? v r(i set ) = 6.49 k ? ref_clk output 50 mhz rmii clock output jitter ??300?ps peak-to-peak (applies only to ksz8091rnb in rmii - 25 mhz clock mode) 100 mbps mode - industrial applications parameters clock phase delay ? xi input to mii txc output ? 152025ns xi (25 mhz clock input) to mii txc (25 mhz clock outp ut) delay, refer- enced to rising e dges of both clocks. (applies only to ksz8091mnx in mii mode) link loss reaction (indication) time t llr ?4.4? s link loss detected at receive differen- tial inputs to phy signal indication time for each of the following: 1. for led mode 00 (ksz8091rnb only), speed led output changes from low (100 mbps) to high (10 mbps, default state for link-down). 2. for led mode 01, link led output changes from low (link-up) to high (link-down). 3. intrp pin asserts for link-down status change. table 6-1: electrical characteristics (continued) parameters symbol min. typ. max. units note
ksz8091mnx/rnb ds00002275a-page 60 ? 2016 microchip technology inc. 7.0 timing diagrams 7.1 mii sqe timing (10base-t) figure 7-1: mii sqe timing (10base-t) table 7-1: mii sqe timing (10base-t) parameters parameter description min. typ. max. units t p txc period ? 400 ? ns t wl txc pulse width low ? 200 ? ns t wh txc pulse width high ? 200 ? ns t sqe col (sqe) delay after txen de-asserted ? 2.2 ? s t sqep col (sqe) pulse duration ? 1.0 ? s t wl t wh t p t sqe t sqep txc txen col
? 2016 microchip technology inc. ds00002275a-page 61 ksz8091mnx/rnb 7.2 mii transmit timing (10base-t) figure 7-2: mii transm it timing (10base-t) table 7-2: mii transmit timing (10base-t) parameters parameter description min. typ. max. units t p txc period ? 400 ? ns t wl txc pulse width low ? 200 ? ns t wh txc pulse width high ? 200 ? ns t su1 txd[3:0] setup to rising edge of txc 120 ? ? ns t su2 txen setup to rising edge of txc 120 ? ? ns t hd1 txd[3:0] hold from rising edge of txc 0 ? ? ns t hd2 txen hold from rising edge of txc 0 ? ? ns t crs1 txen high to crs asserted latency ? 600 ? ns t crs2 txen low to crs de-asserted latency ? 1.0 ? s crs txen txd[3:0] txc t crs1 t wl t p t hd2 t crs2 t wh t hd1 t su2 t su1
ksz8091mnx/rnb ds00002275a-page 62 ? 2016 microchip technology inc. 7.3 mii receive timing (10base-t) figure 7-3: mii receive timing (10base-t) table 7-3: mii receive timing (10base-t) parameters parameter description min. typ. max. units t p rxc period ? 400 ? ns t wl rxc pulse width low ? 200 ? ns t wh rxc pulse width high ? 200 ? ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc ?205? ns t rlat crs to (rxdv, rxd[ 3:0]) latency ? 7.2 ? s crs rxdv rxd[3:0] rxer rxc t rlat t od t p t wl t wh
? 2016 microchip technology inc. ds00002275a-page 63 ksz8091mnx/rnb 7.4 mii transmit timing (100base-tx) figure 7-4: mii transmit timing (100base-tx) table 7-4: mii transmit timing (100base-tx) parameters parameter description min. typ. max. units t p txc period ? 40 ? ns t wl txc pulse width low ? 20 ? ns t wh txc pulse width high ? 20 ? ns t su1 txd[3:0] setup to rising edge of txc 10 ? ? ns t su2 txen setup to rising edge of txc 10 ? ? ns t hd1 txd[3:0] hold from rising edge of txc 0 ? ? ns t hd2 txen hold from rising edge of txc 0 ? ? ns t crs1 txen high to crs asserted latency ? 72 ? ns t crs2 txen low to crs de-asserted latency ? 72 ? ns crs txen txd[3:0] txc t crs1 t wl t p t hd1 t su1 t crs2 data in t wh t hd2 t su2
ksz8091mnx/rnb ds00002275a-page 64 ? 2016 microchip technology inc. 7.5 mii receive timing (100base-tx) figure 7-5: mii receive timing (100base-tx) table 7-5: mii receive timing (10base-t) parameters parameter description min. typ. max. units t p rxc period ? 40 ? ns t wl rxc pulse width low ? 20 ? ns t wh rxc pulse width high ? 20 ? ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 16 21 25 ns t rlat crs to (rxdv, rxd[3:0]) latency ? 170 ? ns crs rxdv rxd[3:0] rxer rxc t rlat t od t p t wl t wh
? 2016 microchip technology inc. ds00002275a-page 65 ksz8091mnx/rnb 7.6 rmii timing note 7-1 25 mhz input to xi pin, 50 mhz output from ref_clk pin. note 7-1 50 mhz input to xi pin. figure 7-6: rmii timing - data received from rmii figure 7-7: rmii timing - data input to rmii table 7-6: rmii timing parameters - ksz8091rnb ( note 7-1 ) timing parameter description min. typ. max. units t cyc clock cycle ? 20 ? ns t 1 setup time 4 ? ? ns t 2 hold time 2 ? ? ns t od output delay 7 10 13 ns table 7-7: rmii timing parameters - ksz8091rnb ( note 7-1 ) timing parameter description min. typ. max. units t cyc clock cycle ? 20 ? ns t 1 setup time 4 ? ? ns t 2 hold time 2 ? ? ns t od output delay 8 11 13 ns t cyc ref_clk txen txd[1:0] t 1 t 2 transmit timing t cyc ref_clk crs_dv rxd[1:0] rxer t od receive timing
ksz8091mnx/rnb ds00002275a-page 66 ? 2016 microchip technology inc. 7.7 auto-negotiation timing figure 7-8: auto-negotiation fast link pulse (flp) timing table 7-8: auto-negotiation fast link pulse timing parameters parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width ? 2 ? ms t pw clock/data pulse width ? 100 ? ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s ? number of clock/data pulses per flp burst 17 ? 33 ? auto -negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst
? 2016 microchip technology inc. ds00002275a-page 67 ksz8091mnx/rnb 7.8 mdc/mdio timing figure 7-9: mdc/mdio timing table 7-9: mdc/mdio timing parameters parameter description min. typ. max. units f c mdc clock frequency ? 2.5 10 mhz t p mdc period ? 400 ? ns t md1 mdio (phy input) setup to rising edge of mdc 10 ? ? ns t md2 mdio (phy input) hold from rising edge of mdc 4 ? ? ns t md3 mdio (phy output) delay from rising edge of mdc 5 222 ? ns t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p
ksz8091mnx/rnb ds00002275a-page 68 ? 2016 microchip technology inc. 7.9 power-up/reset timing the ksz8091mnx/rnb reset timing requirement is summarized in figure 7-10 and ta b l e 7 - 1 0 . the supply voltage (v ddio and v dda_3.3 ) power-up waveform should be monotonic. the 300 s minimum rise time is from 10% to 90%. for warm reset, the reset (rst#) pin should be asserted low for a minimum of 500 s. the strap-in pin values are read and updated at the de-assertion of reset. after the de-assertion of reset, wait a minimum of 100 s before starting programming on the miim (mdc/mdio) inter- face. figure 7-10: power-up/reset timing table 7-10: power-up/reset timing parameters parameter description min. typ. max. units t vr supply voltage (v ddio , v dda_3.3 ) rise time 300 ? ? s t sr stable supply voltage (v ddio , v dda_3.3 ) to reset high 10 ? ? ms t cs configuration setup time 5 ? ? ns t ch configuration hold time 5 ? ? ns t rc reset to strap-in pin output 6 ? ? ns supply voltages rst# strap-in value strap-in / output pin t vr t sr t cs t ch t rc
? 2016 microchip technology inc. ds00002275a-page 69 ksz8091mnx/rnb 8.0 reset circuit figure 8-1 shows a reset circuit recommended for powering up t he ksz8091mnx/rnb if reset is triggered by the power supply. figure 8-1: recommended reset circuit figure 8-2 shows a reset circuit recommended for applications w here reset is driven by another device (for example, the cpu or an fpga). the reset out rst_out_n from cp u/fpga provides the warm reset after power up reset. d2 is used if using different v ddio between the switch and cpu/fp ga, otherwise, the different v ddio will fight each other. if different v ddio have to use in a special case, a low v f (<0.3v) diode is required (for example, vishay?s bat54, mss1p2l and so on), or a level shifter device can be us ed too. if ethernet device and cpu/fpga use same v ddio voltage, d2 can be removed to connect both devices dire ctly. usually, ethernet device and cpu/fpga should use same v ddio voltage. figure 8-2: recommended reset circuit for cpu/fpga reset output vddio d1: 1n4148 d1 r 10k ? ksz8091mnx/rnb rst# c 10f vddio ksz8091mnx/rnb d1 r 10k ? rst# c 10f d2 cpu/fpga rst_out_n d1: 1n4148
ksz8091mnx/rnb ds00002275a-page 70 ? 2016 microchip technology inc. 9.0 reference circuits ? led strap-in pins the pull-up, float, and pull-down reference circuits for the led1/speed and led0/p me_n1/nwayen strapping pins are shown in figure 9-1 for 3.3v and 2.5v v ddio . figure 9-1: reference circuits for led strapping pins for 1.8v v ddio , led indication support is not recommended due to the low voltage. without the led indicator, the speed and nwayen strap-in pins are functional with a 4.7 k ? pull-up to 1.8v v ddio or float for a value of ?1?, and with a 1.0 k ? pull-down to ground for a value of ?0?. if using rj45 jacks with int egrated leds and 1.8v v ddio , a level shifting is required from led 3.3v to 1.8v. for example, use a bipolar transistor or a level shift device. led pin 220 ? 4.7k ? pull_up ksz8091mnx/rxb vddio = 3.3v, 2.5v led pin 220 ? float ksz8091mnx/rxb vddio = 3.3v, 2.5v led pin 220 ? pull-down ksz8091mnx/rxb vddio = 3.3v, 2.5v 1k ?
? 2016 microchip technology inc. ds00002275a-page 71 ksz8091mnx/rnb 10.0 reference clock - co nnection and selection a crystal or external clock source, such as an oscillator, is used to provid e the reference clock for the ksz8091mnx/ rnb. for the ksz8091mnx/rnb in all operating modes and for the ksz8091rnb in rmii - 25 mhz clock mode, the reference clock is 25 mhz. the reference clock connections to xi (pin 9) and xo (pin 8), and the reference clock selec- tion criteria, are provided in figure 10-1 and table 10-1 . figure 10-1: 25 mhz crystal/oscillator reference clock connection note 10-1 60 ppm for overtemperature crystal. for the ksz8091rnb in rmii - 50 mhz clock mode, the refe rence clock is 50 mhz. the reference clock connections to xi (pin 9), and the reference clo ck selection criteria are provided in figure 10-2 and table 10-2 . table 10-1: 25 mhz crystal/refer ence clock selection criteria characteristics value frequency 25 mhz frequency tolerance (max.); note 10-1 50 ppm crystal series resistance (typ.) 40 ? crystal load capacitance (typ.) 16 pf figure 10-2: 50 mhz oscillator reference clock connection table 10-2: 50 mhz oscillator/ref erence clock selection criteria characteristics value frequency 50 mhz frequency tolerance (max.) 50 ppm nc xi xo 25mhz osc 50ppm xi xo 25mhz xtal 50ppm 22pf 22pf nc xi xo 50mhz osc 50ppm
ksz8091mnx/rnb ds00002275a-page 72 ? 2016 microchip technology inc. 11.0 magnetic - connec tion and selection a 1:1 isolation transformer is required at the line interfac e. use one with integrated common-mode chokes for designs exceeding fcc requirements. the ksz8091mnx/rnb design incorporates voltag e-mode transmit drivers and on-chip terminations. with the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs. therefore, the two transformer center tap pins on the ksz8091mnx/rnb side should not be connected to any power supply source on the board; inst ead, the center tap pins should be sepa rated from one another and connected through separate 0.1 f common-mode capacitors to groun d. separation is required because the common-mode volt- age is different between transmitting and receiving differential pairs. figure 11-1 shows the typical magnetic interface circuit for the ksz8091mnx/rnb. figure 11-1: typical magnetic interface circuit table 11-1 lists recommended magnetic characteristics. table 11-1: magnetics selection criteria parameter value test conditions turns ratio 1 ct : 1 ct ? open-circuit inductance (min.) 350 h 100 mv, 100 khz, 8 ma insertion loss (max.) ?1.1 db 100 khz to 100 mhz hipot (min.) 1500 v rms ? 1 2 3 7 8 4 5 6 4 x 75 ? 1000pf/2kv rj-45 connector chassis ground (2 x 0.1f) txp txm rxp rxm ksz8091mnx/rnb signal ground
? 2016 microchip technology inc. ds00002275a-page 73 ksz8091mnx/rnb table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the phy chip side that can be used wit h the ksz8091mnx/rnb. table 11-2: compatible single-port 10/100 magnetics manufacturer part number temperature range magnetic + rj-45 bel fuse s558-5999-u7 0c to 70c no bel fuse si-46001-f 0c to 70c yes bel fuse si-50170-f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11-2450e 0c to 70c yes halo tg110-e055n5 ?40c to 85c no lankom lf-h41s-1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 ?40c to 85c no pulse j00-0014 0c to 70c yes pulse jx0011d21nl ?40c to 85c yes tdk tla-6t718a 0c to 70c yes transpower hb726 0c to 70c no wurth/midcom 000-7090-37r-lf1 ?40c to 85c no
ksz8091mnx/rnb ds00002275a-page 74 ? 2016 microchip technology inc. 12.0 package outline figure 12-1: 32-lead qfn 5 mm x 5 mm package note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging.
? 2016 microchip technology inc. ds00002275a-page 75 ksz8091mnx/rnb appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00002275a (09-15-16) ? converted micrel data s heet ksz8091mnx/rnb to microchip ds00002275a. minor text changes throughout.
ksz8091mnx/rnb ds00002275a-page 76 ? 2016 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
? 2016 microchip technology inc. ds00002275a-page 77 ksz8091mnx/rnb product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: ksz8091 interface: m = mii r = rmii package: n = 32-pin qfn special attribute: b = 25 mhz in/50 mhz out clocks x = none temperature: ca = 0 ? c to +70 ? c (commercial) ia = ?40 ? c to +85 ? c (industrial) media type: blank = tray tr = tape & reel examples: a) ksz8091mnxca mii interface 32-pin qfn no special attribute commercial temperature tray b) ksz8091mnxia mii interface 32-pin qfn no special attribute industrial temperature tray c) ksz8091mnxca-tr mii interface 32-pin qfn no special attribute commercial temperature tape & reel d) ksz8091mnxia-tr mii interface 32-pin qfn no special attribute industrial temperature tape & reel e) ksz8091rnbca rmii interface 32-pin qfn 25 mhz in/50 mhz out clocks commercial temperature tray f) ksz8091rnbia rmii interface 32-pin qfn 25 mhz in/50 mhz out clocks industrial temperature tray g) ksz8091rnbca-tr rmii interface 32-pin qfn 25 mhz in/50 mhz out clocks commercial temperature tape & reel h) ksz8091rnbia-tr rmii interface 32-pin qfn 25 mhz in/50 mhz out clocks industrial temperature tape & reel part no. x x package interface device xx temperature x special attribute xx media type
ksz8091mnx/rnb ds00002275a-page 78 ? 2016 microchip technology inc.
? 2016 microchip technology inc. ds00002275a-page 79 information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpw r, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, re al ice, ripple blocker, serial quad i/o, sqi, superswitcher, super switcher ii, total endurance, ts harc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0944-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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